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Journals

2011
  1. M. Ahmadi, A. Shahbahrami, S. Wong, Collaboration of reconfigurable processors in grid computing: Theory and application, Journal of Future Generation Computer Systems, pp. 850-859, June 2011 (BibTeX)
  2. M. Ahmadi, S. Wong, A Cache Architecture for Counting Bloom Filters: Theory and Application, Journal of Electrical and Computer Engineering, June 2011 (BibTeX)
2010
  1. F. Duarte, S. Wong, Cache-Based Memory Copy Hardware Accelerator for Multi-Core Systems, IEEE Transactions on Computers, pp. 1494-1507, November 2010, volume 59, issue 11 (BibTeX)
2008
  1. J.Y. Hur, S. Wong, T. P. Stefanov, Design Trade-offs in Customized On-chip Crossbar Schedulers, Journal of Signal Processing Systems (on-line), ISSN number 1939-8018, September 2008 (BibTeX)
  2. J.Y. Hur, S. Wong, S. Vassiliadis, Partially reconfigurable point-to-point FPGA interconnects, International Journal of Electronics, vol. 95, no. 7, pp. 725-742, July 2008 (BibTeX)
  3. C. Kachris, S. Wong, S. Vassiliadis, Design and Performance Evaluation of an Adaptive FPGA for Network Applications, Microelectronics Journal, pp. 1-8, July 2008, doi:10.1016/j.mejo.2008.05.011 (BibTeX)
  4. K. Tatas, T. Trancoso, E. Evripidou, S. Wong, Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs, Parallel Processing Letters (PPL),Vol: 18 Issue: 2, pp. 291-306, June 2008, DOI: 10.1142/S0129626408003399 (BibTeX)
2006
  1. L. Mhamdi, M. Hamdi, C. Kachris, S. Wong, S. Vassiliadis, High-performance switching based on buffered crossbar fabrics, Computer Networks Journal, pp. 2271-2285, September 2006, Vol. 50, No. 13 (BibTeX)
2004
  1. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K.L.M. Bertels, G. Kuzmanov, E. Moscu Panainte, The Molen Polymorphic Processor, IEEE Transactions on Computers, pp. 1363- 1375, November 2004, Volume 53, Issue 11 (BibTeX)
2003
  1. S. Vassiliadis, S. Wong, S. D. Cotofana, Microcode Processing: Positioning and Directions, IEEE Micro, vol. 23, no. 4, pp. 21-30, July 2003 (BibTeX)

Book Chapters

2011
  1. S. Wong, L Carro, M. B. Rutzig, D Matos, R. Giorgi, N. Puzovic, S Kaxiras, , G Desoli, , ERA - Embedded Reconfigurable Architectures, Chapter 5 in Reconfigurable Computing - From FPGAs to Hardware/Software Codesign, pp. 239--260, Springer, August 2011, ISBN: 978-1-4614-0060-8 (BibTeX)
2004
  1. S. Wong, S. Vassiliadis, S. D. Cotofana, Future Directions of Programmable and Reconfigurable Embedded Processors, Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, pp. 235-257, January 2004 (BibTeX)

Conference Proceedings

2012
  1. F. Anjam, Q Kong, RAE Seedorf, S. Wong, A Run-time Task Migration Scheme for an Adjustable Issue-slots Multi-core Processor, To appear in the 8th International Symposium on Applied Reconfigurable Computing (ARC), Hong Kong, March 2012 (BibTeX)
  2. F. Anjam, Q Kong, RAE Seedorf, S. Wong, On the Implementation of Traps for a Softcore VLIW Processor, To appear in HiPEAC Workshop on Reconfigurable Computing (WRC) , Paris, France, January 2012 (BibTeX)
  3. RAE Seedorf, F. Anjam, A.A.C. Brandon, S. Wong, Design of a Pipelined and Parameterized VLIW Processor: r-VEX v.2.0, To appear in HiPEAC Workshop on Reconfigurable Computing (WRC) , Paris, France, January 2012 (BibTeX)
2011
  1. M.F. Nadeem, S. A. Ostadzadeh, M Nadeem, S. Wong, K.L.M. Bertels, A Simulation Framework for Reconfigurable Processors in Large-scale Distributed Systems, (To appear in) International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS), International Conference on Parallel Processing (ICPP), Taiwan, September 2011 (BibTeX)
  2. M.F. Nadeem, S. A. Ostadzadeh, S. Wong, K.L.M. Bertels, Task Scheduling Strategies for Dynamic Reconfigurable Processors in Distributed Systems, in the proceedings of the 2011 International Conference on High Performance Computing & Simulation (HPCS 2011), pp. 8, Istanbul, Turkey, July 2011 (BibTeX)
  3. S. Wong, A.A.C. Brandon, F. Anjam, RAE Seedorf, R. Giorgi, N. Puzovic, S. McKee, L Carro, G. Keramidas, Early Results from ERA – Embedded Reconfigurable Architectures, Proceedings of the IEEE 9th International Conference on Industrial Informatics (INDIN), pp. 816-822, Lisbon, Portugal, July 2011 (BibTeX)
  4. M Nadeem, S. Wong, G. Kuzmanov, An Efficient Hardware Design for Intra-prediction in H.264/AVC Decoder, Saudi International Electronics, Communications and Photonics Conference (SIECPC), Riyadh, Saudi Arabia , April 2011 (BibTeX)
  5. F. Anjam, M Nadeem, S. Wong, Targeting Code Diversity with Run-time Adjustable Issue-slots in a Chip Multiprocessor, Proceedings of the Design, Automation and Test in Europe Conference (DATE 2011), Grenoble, France, March 2011 (BibTeX)
  6. L Sterpone, D Matos, L Carro, S. Wong, F. Anjam, A New Reconfigurable Clock-gating Technique for Low Power SRAM-based FPGAs, Proceedings of the Design, Automation and Test in Europe Conference (DATE 2011), Grenoble, France, March 2011 (BibTeX)
  7. M Nadeem, S. Wong, G. Kuzmanov, Inverse Integer Transform in H.264/AVC Intra-frame Encoder, International Symposium on Electronic Design, Test and Applications (DELTA), pp. 228 -- 233, Queenstown, New Zeeland, January 2011 (BibTeX)
  8. M.F. Nadeem, S. A. Ostadzadeh, M. Ahmadi, M Nadeem, S. Wong, A Novel Dynamic Task Scheduling Algorithm for Grid Networks with Reconfigurable Processors, HiPEAC Workshop on Reconfigurable Computing (WRC), Heraklion, Crete, GREECE, January 2011 (BibTeX)
2010
  1. M Nadeem, S. Wong, G. Kuzmanov, M. Shabbir, F. Anjam, M.F. Nadeem, Low-power, High-throughput Deblocking Filter for H.264/AVC, International Symposium on System-on-Chip (SoC), pp. 93--98, Tampere, Finland, September 2010 (BibTeX)
  2. N. Puzovic, S. McKee, R. Eres, Ayal Zaks, P. Gai, S. Wong, R. Giorgi, A Multi-Pronged Approach to Benchmark Characterization, IEEE International Conference on Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), pp. 1--4, Heraklion, Greece, September 2010 (BibTeX)
  3. M Nadeem, S. Wong, G. Kuzmanov, An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder, International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pp. 71--78, Samos, Greece, July 2010 (BibTeX)
  4. M. Ahmadi, A. Shahbahrami, S. Wong, Collaboration of Reconfigurable Processors in Grid Computing for Multimedia Kernels, Proceedings of the 5th International Conference on Grid and Pervasive Computing, Hualien, Taiwan, May 2010 (BibTeX)
  5. F. Anjam, S. Wong, M.F. Nadeem, A shared Reconfigurable VLIW Multiprocessor System, 17th Reconfigurable Architecture Workshop (RAW 2010), Atlanta, Geogia, USA, April 2010 (BibTeX)
  6. S. Wong, F. Anjam, M.F. Nadeem, Dynamically Reconfigurable Register File for a Softcore VLIW Processor, Proceedings of the Design, Automation and Test in Europe Conference (DATE 2010), Dresden, Germany, March 2010 (BibTeX)
  7. F. Anjam, M Nadeem, S. Wong, A VLIW Softcore Processor with Dynamically Adjustable Issue-slots, International Conference on Field-Programmable Technology (FPT), Beijing, China, December 2010 (BibTeX)
  8. F. Anjam, S. Wong, M.F. Nadeem, A Multiported Register File with Register Renaming for Configurable Softcore VLIW Processors, International Conference on Field Programmable Technology (FPT), Beijing, China, December 2010 (BibTeX)
  9. M.F. Nadeem, M. Ahmadi, M Nadeem, S. Wong, Modeling and Simulation of Reconfigurable Processors in Grid Networks, International Conference on ReConFigurable Computing and FPGAs (ReConFig 2010), Cancun, Mexico, December 2010 (BibTeX)
  10. M Nadeem, S. Wong, G. Kuzmanov, Configurable, Low-power Design for Inverse Integer Transform in H.264/AVC, International Conference on Frontiers of Information Technology (FIT), Islamabad, Pakistan, December 2010 (BibTeX)
  11. R. Hassanpour, A. Shahbahrami, S. Wong, Hand Segmentation by Fusing 2D and 3D Data, The 2nd International Conference on Computer modeling and simulation (iccms 2010), January 2010 (BibTeX)
2009
  1. M. Ahmadi, S. Wong, K-Stage Pipelined Bloom Filter for Packet Classification, The 7th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC-09), pp. 64-70, Vancouver, Canada, August 2009 (BibTeX)
  2. R. Choupani, S. Wong, M. Tolun, Multiple Description Scalable Coding for Video Transmission over Unreliable Networks, proceedings of the International Symposium on Systems, Architectures, MOdeling and Simulation, Samos, Greece, July 2009 (BibTeX)
  3. R. Choupani, S. Wong, M. Tolun, A Drift-Reduced Hierarchical Wavelet Coding Scheme for Scalable Video Transmissions, First International Conference on Advances in Multimedia, Colmar, France, July 2009 (BibTeX)
  4. A. Shahbahrami, M. Ahmadi, S. Wong, K.L.M. Bertels, A New Approach to Implement Discrete Wavelet Transform using Collaboration of Reconfigurable Elements, proceedings of international conference on ReConFigurable Computing and FPGAs, pp. 344-349, Cancun, Mexico, December 2009 (BibTeX)
  5. S. Wong, F. Anjam, The Delft Reconfigurable VLIW Processor, 17th International Conference on Advanced Computing and Communications (ADCOM 2009), pp. 244-251, Bangalore, India, December 2009, Invited Paper (BibTeX)
  6. M Nadeem, S. Wong, G. Kuzmanov, A. Shabbir, A High-Throughput, Area-Efficient Hardware Accelerator for Adaptive Deblocking Filter in H.264/AVC, 7th IEEE Workshop on Embedded systems for Real-time Multimedia (ESTIMedia 2009), pp. 18-27, Grenoble, France, October 2009 (BibTeX)
2008
  1. R. Choupani, S. Wong, M. Tolun, Weighted Embedded Zero Tree for Scalable Video Compression, Proc. Int. Conf. on Image Processing, Computer Vision, and Pattern Recognition (IPCV08), Las Vegas, Nevada, USA, July 2008 (BibTeX)
  2. R. Hassanpour, A. Shahbahrami, S. Wong, Adaptive Gaussian Mixture Model for Skin Color Segmentation, Proceedings of World Academy of Science, Engineering and Technology, Vol. 31, ISSN 1307-6884, pp. 1-6, Vienna, Austria, July 2008 (BibTeX)
  3. R. Hassanpour, S. Wong, A. Shahbahrami, Vision-Based Hand Gesture Recognition for Human Computer Interaction: A Review, IADIS International Conference Interfaces and Human Computer Interaction 2008, ISBN:978-972-8924-59-1, pp. 125-134, Amsterdam, the Netherlands, July 2008 (BibTeX)
  4. M. Ahmadi, S. Wong, An Approach for Optimal Bandwidth Allocation in Packet Processing systems, Proceedings of sixth Annual IEEE/ACM conference on Communication Networks and Services Research 2008 (CNSR 2008), pp. 208-214, Halifax, Canada, May 2008 (BibTeX)
  5. O.S. Dragomir, E. Moscu Panainte, K.L.M. Bertels, S. Wong, Optimal Unroll Factor for Reconfigurable Architectures, Proceedings of the 4th International Workshop on Applied Reconfigurable Computing, London, UK, March 2008 (BibTeX)
  6. S. Wong, T. van As, G. Brown, ρ-VEX: A Reconfigurable and Extensible Softcore VLIW Processor, International Conference on Field-Programmable Technology (ICFPT), Taipei, Taiwan, December 2008 (BibTeX)
  7. M. Ahmadi, S. Wong, A Memory-optimized Bloom Filter using An Additional Hashing Function, Accepted for publication to appear in proceedings of IEEE Globecom 2008 Next Generation Networks, Protocols, and Services Symposium, New Orleans, USA, December 2008 (BibTeX)
  8. M. Ahmadi, S. A. Ostadzadeh, S. Wong, Rule-set Database Inspection: Towards Data Utilization in Packet Processing, Proceedings of International Conference on the Latest Advances in Networks, Toulouse, France, December 2008 (BibTeX)
  9. S. Wong, M. Ahmadi, Reconfigurable Architectures in Collaborative Grid Computing: An Approach, Proceedings of the Second International conference on Networks for Grid Applications (GridNets 2008), Beijing, China, October 2008 (BibTeX)
2007
  1. S.D. Breijer, F. Duarte, S. Wong, An OCM Based Shared Memory Controller For Virtex 4, Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 692--696, Amsterdam, The Netherlands, August 2007 (BibTeX)
  2. S. Vassiliadis, F. Duarte, S. Wong, A Load/Store Unit for a memcpy Hardware Accelerator, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 537--541, Amsterdam, The Netherlands, August 2007 (BibTeX)
  3. S.J. Raaijmakers, S. Wong, Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), Amsterdam, The Netherlands, August 2007 (BibTeX)
  4. R. Guo, J. G. Delgado-Frias, S. Wong, Cache Replacement Policies for IP Address Lookups, Proceedings of The Fifth IASTED International Conference on Circuits, Signals, and Systems, pp. 70-75, Banff, Alberta, Canada, July 2007 (BibTeX)
  5. J.Y. Hur, T. P. Stefanov, S. Wong, S. Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler, IEEE 18th International Conference on Application-specific Systems, Architectures and Processors (ASAP07), Montreal, Canada, July 2007 (BibTeX)
  6. F. Duarte, S. Wong, A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies, Proceedings of 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP07), Montréal, Canada, July 2007 (BibTeX)
  7. J.Y. Hur, T. P. Stefanov, S. Wong, S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects, Proceedings of international workshop on applied reconfigurable computing (ARC07), In LNCS 4419, pp. 61-72, Rio de Janeiro, Brazil, March 2007 (BibTeX)
  8. J.Y. Hur, S. Wong, S. Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs, Proceedings of international workshop on applied reconfigurable computing (ARC07), In LNCS 4419, pp. 49-60, Rio de Janeiro, March 2007 (BibTeX)
  9. M. Ahmadi, S. Wong, Modified Collision Packet Classification Using CountingBloom Fillter In Tuple Space, Proceedings of the 25th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2007), pp. 70-76, Innsbruck, Austria, February 2007 (BibTeX)
  10. M. Ahmadi, S. Wong, Hashing Functions Performance in Packet Classification, Proceedings of International Conference on the Latest Advances in Networks (ICLAN-2007), pp. 127-132, Paris, France, December 2007 (BibTeX)
  11. M. Ahmadi, S. Wong, A Cache Architecture for Counting Bloom Filters, Proceedings of 15th IEEE International Conference on Networks (ICON2007), pp. 218-223, Adelaide, Australia, November 2007 (BibTeX)
  12. M. Ahmadi, S. Wong, A Performance Model for Network Processor Architectures in Packet Processing Systems, Proceedings of the 19th International Conference on Parallel and Distributed Computing and Systems (PDCS 2007), pp. 176-181, Cambridge, Massachusetts, USA, November 2007 (BibTeX)
2006
  1. J.C.B. de Mattos, S. Wong, L. Carro, The Molen FemtoJava Engine, Proceedings of the 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP2006), pp. 19-22, USA, September 2006 (BibTeX)
  2. F. Duarte, S. Wong, Profiling Bluetooth and Linux on the Xilinx Virtex II Pro, Proceedings of 9th Euromicro Conference on Digital System Design (DSD06), pp. 229-235, Dubrovnik, Croatia, August 2006 (BibTeX)
  3. S. Vassiliadis, G. Kuzmanov, S. Wong, E. Moscu Panainte, G. N. Gaydadjiev, K.L.M. Bertels, h Cheresiz, PISC: Polymorphic Instruction Set Computers, Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC 2006), pp. 274-286, Delft, The Netherlands, March 2006, LNCS 3985 (BibTeX)
  4. S. Wong, F. Duarte, S. Vassiliadis, A Hardware Cache memcpy Accelerator, Proceedings of IEEE International Conference on Field Programmable Technology (FPT06), pp. 141-147, Bangkok, Thailand, December 2006 (BibTeX)
2005
  1. I. Sourdis, D.N. Pnevmatikatos, S. Wong, S. Vassiliadis, A Reconfigurable Perfect-Hashing Scheme for Packet Inspection, proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp. 644-647, Tampere, Finland, August 2005 (BibTeX)
2003
  1. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K.L.M. Bertels, Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers, IEE FPGA Developer's Forum, London, United Kingdom, October 2003, (invited talk) (BibTeX)
2002
  1. S. Wong, S. Vassiliadis, S. D. Cotofana, A Sum of Absolute Differences Implementation in FPGA Hardware, in Proceedings of the 28th EUROMICRO Conference, pp. 183-188, Dortmund, Germany, September 2002 (BibTeX)
  2. S. Wong, S. Vassiliadis, S. D. Cotofana, Future Directions of (Programmable and Reconfigurable) Embedded Processors, in Proceedings of the SAMOS 2002 Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, Samos, Greece, July 2002 (BibTeX)
  3. S. Wong, S. D. Cotofana, On Teaching Embedded Systems Design to Electrical Engineering Students, in Proceedings of 3rd International Conference on Information Communication Technologies in Education (ICICTE2002), pp. 505-515, Samos, Greece, July 2002 (BibTeX)
  4. S. Wong, B. Stougie, S. D. Cotofana, Alternatives in FPGA-based SAD Implementations, in Proceedings of the 1st IEEE International Conference on Field-Programmable Technology (FPT2002), pp. 449-452, Hong Kong SAR, China, December 2002 (BibTeX)
2001
  1. S. Vassiliadis, G. Kuzmanov, S. Wong, MPEG-4 and the New Multimedia Architectural Challenges, in Proceedings of the 15th International conference on Systems for automation of engineering and research (SAER-2001), pp. 24-32, Varna, Bulgaria, September 2001 (BibTeX)
  2. S. Vassiliadis, S. Wong, S. D. Cotofana, The MOLEN -coded Processor, in 11th International Conference on Field-Programmable Logic and Applications (FPL), Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2147, pp. 275-285, Belfast, UK, August 2001 (BibTeX)
  3. S. Wong, S. Vassiliadis, S. D. Cotofana, Microcoded Reconfigurable Embedded Processors: Current Developments, Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2268, pp. 207-224, Samos, Greece, July 2001 (BibTeX)
  4. S. Vassiliadis, S. Wong, S. D. Cotofana, Network Processors: Issues and Prospectives, in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-2001), pp. 1827-1833, Las Vegas, NV, USA, June 2001 (BibTeX)
  5. S. Wong, S. D. Cotofana, S. Vassiliadis, Coarse Reconfigurable Multimedia Unit Extension, Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing (PDP 2001), pp. 235-242, Mantova, Italy, February 2001 (BibTeX)
2000
  1. S. Wong, S. D. Cotofana, S. Vassiliadis, Multimedia Enhanced General-Purpose Processors, Proceedings of the International Conference on Multimedia and Expo, pp. 1-4, New York City, NY, USA, July 2000 (BibTeX)
  2. S. Wong, S. D. Cotofana, S. Vassiliadis, General-Purpose Processor Huffman Encoding Extension, Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2000), pp. 158-163, Las Vegas, Nevada, March 2000 (BibTeX)
1998
  1. S. Vassiliadis, E. A. Hakkennes, S. Wong, G. G. Pechanek, The Sum-of-Absolute-Difference Motion Estimation Accelerator, in Proceedings of the 24th Euromicro Conference, pp. 559-566, Vasteras, Sweden, August 1998 (BibTeX)

Local Conference Proceedings

2012
  1. J.Y. Hur, T. P. Stefanov, S. Wong, K.G.W. Goossens, Customisation of on-chip network interconnects and experiments in field-programmable gate arrays, Journal of IET Computers & Digital Techniques vol 6, issue 1, pp. 59-68, January 2012, ISSN: 1751-8601 (BibTeX)
2010
  1. M.F. Nadeem, F. Anjam, S. A. Ostadzadeh, M. Ahmadi, S. Wong, Towards the Utilization of Reconfigurable Processors in Grid Networks, In the proceedings of the 21th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2010), Veldhoven, The Netherlands, November 2010 (BibTeX)
2008
  1. M. Ahmadi, S. Wong, On incorporating Reconfigurable Architectures into Grid environments using GridSim, Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), Veldhoven, The Netherlands,, November 2008 (BibTeX)
  2. A. Shahbahrami, J.Y. Hur, B.H.H. Juurlink, S. Wong, FPGA Implementation of Parallel Histogram Computation, 2nd HiPEAC Workshop on Reconfigurable Computing, pp. 63-72, Göteborg, SWEDEN, January 2008 (BibTeX)
2007
  1. M. Ahmadi, S. A. Ostadzadeh, S. Wong, An Analysis of Rule-set Databases in Packet Classification, Proceedings of the 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), Veldhoven, The Netherlands, November 2007 (BibTeX)
  2. F. Duarte, S. Wong, Analysis of a User-space Device-driver for the memcpy Hardware, Proceedings of the 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC07), Veldhoven, The Netherlands, November 2007 (BibTeX)
  3. F. Duarte, S.D. Breijer, S. Wong, Supporting the Linux Operating System on the MOLEN Processor Prototype, Proceedings of the 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC07), Veldhoven, The Netherlands, November 2007 (BibTeX)
2006
  1. D. Ludovici, S. Wong, Performance Analysis of RR and FQ Algorithms in Reconfigurable Routers, Proceedings of the 17th Annual Workshop on Circuits, Systems and Signal Processing. ProRisc 2006, Veldhoven, The Netherlands, November 2006 (BibTeX)
  2. M. Ahmadi, S. Wong, Network Processors: Challenges and Trends, Proceedings of the 17th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2006, pp. 222-232, Veldhoven, The Netherlands, November 2006 (BibTeX)
  3. S.J. Raaijmakers, S. Wong, Run-time Placement and Routing on the Virtex 2 Pro, Proceedings of the 17th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2006, pp. 325-329, Veldhoven, The Netherlands, November 2006 (BibTeX)
2005
  1. F. Duarte, S. Wong, Bluetooth protocol profiling on the Xilinx Virtex II Pro, Proceedings of Architectures and Compilers for Embedded Systems (ACES05), Edegem, Belgium, September 2005 (BibTeX)
  2. Y Zhao, S. Wong, Benchmarking and Profiling the RSVP Protocol, Proceedings of the 16th Annual Workshop on Circuits, Systems and, pp. 470-474, Veldhoven, the Netherlands, November 2005 (BibTeX)
  3. S. Wong, S. Vassiliadis, J.Y. Hur, Parallel Merge Sort on a Binary Tree On-Chip Network, Proceedingslocal of the 16th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2005, pp. 365-368, Veldhoven, The Netherlands, November 2005 (BibTeX)
  4. M. van den Braak, S. Wong, FPGA implementation of Voice-over IP, Proceedings of the 16th Annual Workshop on Circuits, Systems and, pp. 338-342, Veldhoven, the Netherlands, November 2005 (BibTeX)
  5. F. Duarte, S. Wong, Bluetooth Profiling on Xilinx Virtex II Pro, Proceedings of the 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC05), pp. 495-499, Veldhoven, The Netherlands, November 2005 (BibTeX)
2004
  1. S. Wong, Y. Wu, Design Challenges in Security Processing, Proceedings of the 15th Annual Workshop on Architecture and System Design (ProRISC2004), pp. 189-194, Veldhoven, The Netherlands, November 2004 (BibTeX)
2003
  1. W. Lu, S. Wong, A Fast CRC Update Implementation, Proceedings of the 14th Annual Workshop on Circuits, Systems and Signal Processing,, pp. 113-120, Veldhoven, The Netherlands, November 2003 (BibTeX)
  2. Y. Wu, S. Wong, S. Vassiliadis, Real-Time Network Processing: An Investigation, Proceedings of the 14th Annual Workshop on Architecture and System Design (ProRISC2003), pp. 589-594, Veldhoven, The Netherlands, November 2003 (BibTeX)
  3. N. D. Manolov, A Gamil, S. Wong, An Investigation into Multicasting, Proceedings of the 14th Annual Workshop on Architecture and System Design (ProRISC2003), pp. 523-528, Veldhoven, The Netherlands, November 2003 (BibTeX)
  4. A. Snirpunas, A. van Wel, S. Wong, Mapping of Motion Estimation on a VLIW Processor Template, Proceedings of the 14th Annual Workshop on Architecture and System Design (ProRISC2003), pp. 571-576, Veldhoven, The Netherlands, November 2003 (BibTeX)
2002
  1. S. Wong, J. van Kester, M. Konstapel, R. Serra, O. Visser, Building Blocks for MPEG Stream Processing, in Proceedings of the 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC2002), pp. 556-560, Veldhoven, The Netherlands, November 2002 (BibTeX)
  2. S. Wong, G. Luo, S. D. Cotofana, Synthetic Benchmark Generator for the MOLEN Processor, in Proceedings of the 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC2002), pp. 561-567, Veldhoven, The Netherlands, November 2002 (BibTeX)
  3. S. Wong, B. Stougie, S. D. Cotofana, An Investigation on FPGA Based SAD Hardware Implementations, in Proceedings of the 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC2002), pp. 568-573, Veldhoven, The Netherlands, November 2002 (BibTeX)
2001
  1. S. D. Cotofana, S. Wong, S. Vassiliadis, Embedded Processors: Characteristics and Trends, in Proceedings of the 7th Annual Conference of the Advanced School for Computing and Imaging (ASCI 2001), pp. 17-24, Heijen, the Netherlands, May 2001 (BibTeX)
  2. S. Wong, S. Vassiliadis, S. D. Cotofana, SAD Implementation in FPGA Hardware, in Proceedings of the 12th Annual Workshop on Circuits, Systems, and Signal Processing (PRORISC2001), pp. 738-742, Veldhoven, The Netherlands, November 2001 (BibTeX)

Technical Reports

2007
  1. R. Choupani, S. Wong, M. Tolun, Video Coding and Transcoding: A Review, pp. 1-21, CE Technical report, September 2007 (BibTeX)
  2. R. Choupani, S. Wong, M. Tolun, Scalable Video Coding: A Technical Report, pp. 1-33, CE Technical report, September 2007 (BibTeX)
2004
  1. S. Wong, S. Vassiliadis, S. D. Cotofana, Embedded Processors: Characteristics and Trends, Technical Report CE-TR-2004-03, Delft, The Netherlands, May 2004 (BibTeX)
2001
  1. S. Vassiliadis, S. Wong, S. D. Cotofana, The MOLEN -coded Processor, Technical Report 1-68340-44(2001)-01, Delft, The Netherlands, January 2001 (BibTeX)