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CONFERENCE PAPERS (1987 - PRESENT)

  1. B.H.H. Juurlink, A. Shahbahrami, S. Vassiliadis, Avoiding Data Conversions in Embedded Media Processors,  20th ACM Symposium on Applied Computing, pp. to appear, Santa Fe, New Mexico, USA, March 2005
     
  2. E. Moscu Panainte, K. Bertels, S. Vassiliadis, Instruction Scheduling for Dynamic Hardware Configurations,  Proceedings of Design, Automation and Test in Europe 2005 (DATE 05), pp. to appear, March 2005
     
  3. E. Moscu Panainte, K. Bertels, S. Vassiliadis, The PowerPC Backend Molen Compiler, in 14th International Conference on Field-Programmable Logic and Applications (FPL), pp. 434-443, Antwerp, Belgium, September 2004, Springer-Verlag Lecture Notes in Computer Science (LNCS),  vol. 3203 
     
  4. G.K. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Visual Data Rectangular Memory, Proceedings of the 10th International Euro-Par Conference (Euro-Par 2004), pp. 760--767, Pisa, Italy, September 2004, LNCS 3149 
     
  5. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Binary Addition based on Single Electron Tunneling Devices,  Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD  proceedings), Munich, Germany, August 2004 
     
  6. C. Hu, S. D. Cotofana, J. Jianfei, Compact Current and Current Noise Models for Single-Electron Tunneling Transistors,  Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD  proceedings), Munich, Germany, August 2004 
     
  7. J. Cheng, C. Hu, S. D. Cotofana, J. Jianfei, SPICE Implementation of a Compact Single Electron Tunneling Transistor Model,  Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD proceedings), August 2004 
     
  8. G. N. Gaydadjiev, S. Vassiliadis, SCISM versus IA-64 Tagging: Differences and Code Density Effects, Proceedings of 10th International Euro-Par Conference, pp. 571-577, Pisa, Italy, August 2004, Springer-Verlag Lecture Notes in Computer Science (LNCS),  vol. 3149 
     
  9. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Scene Management Models and Overlap Tests for Tile-Based Rendering, Proceedings of the EUROMICRO Symposium on Digital System Design, 2004 (DSD 2004)., pp. 424 - 431, Rennes,  FRANCE, August 2004 
     
  10. Z. Al-Ars, M. Herzog, I. Schanstra, A. J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs,  Records IEEE International Workshop on Memory Technology, Design and Testing,  pp. 32-37, San Jose, CA, August 2004 
     
  11. A. J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants,  Records IEEE International Workshop on Memory Technology, Design and Testing, pp. 26-31, San Jose, CA, August 2004 
     
  12. E. Moscu Panainte, K. Bertels, S. Vassiliadis, Dynamic Hardware Reconfigurations: Performance Impact on MPEG2, Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, Samos,  Greece, July 2004 
     
  13. T. Niculiu, S. D. Cotofana, Hierarchical Inteligent Simulation, Proceedings of the International Conference on System Research, Informatics and Cybernetics Volume III: Cognitive, Emotive and Ethical Aspects of Decision Making in Humans and in Artificial Inteligence,  pp. 45-50, Baden-Baden, Germany, July 2004 
     
  14. G.K. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The Virtex II Pro MOLEN Processor, Proceedings of the 4th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2004), pp. 192-202, Samos, Greece, July 2004, LNCS 3133 
     
  15. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Memory Bandwidth Requirements of Tile-Based Rendering,  Proceedings of the Third and Fourth International Workshops SAMOS 2003 and SAMOS 2004 (LNCS 3133), pp. 323-332, Samos, Greece, July 2004 
     
  16. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, Efficient Hardware for Antialiasing Coverage Mask Generation,  Proceedings of Computer Graphics International Conference 2004 (CGI 2004), pp. 257-264, Crete, Greece, June 2004 
     
  17. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, GraalBench: A 3D Graphics Benchmark Suite for Mobile Phones,  Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools, pp. 1-9, Washington, DC, USA, June 2004 
     
  18. D. Crisu, S. Vassiliadis, S. D. Cotofana, P. Liuha, Low Cost and Latency Embedded 3D Graphics Reciprocation,  Proceedings of 2004 IEEE International Symposium on Circuits and Systems (ISCAS  2004), pp. II-905 - II-908, Vancouver, Canada, May 2004 
     
  19. C. Hu, S. D. Cotofana, J. Jianfei, Analysis of Analog to Digital Converter Based on Single Electron Tuneling Transistors,  Proceedings of 2004 IEEE International Symposium on Circuits and Systems (ISCAS  2004), pp. 693-696, Vancouver, Canada, May 2004 
     
  20. A. J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Decoder Delay Faults in RAMs Due to Inter-Gate Opens,  Proceedings of IEEE European Test Symposium, Corsica, France, May 2004 
     
  21. B.H.H. Juurlink, P. J. de Langen, Dynamic Techniques to Reduce Memory Traffic in Embedded Systems,  Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 192-201, Ischia, Italy, April 2004 
     
  22. P. J. de Langen, B.H.H. Juurlink, Reducing Traffic Generated by Conflict Misses in Caches,  Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 235-239, Ischia, Italy, April 2004 
     
  23. B.H.H. Juurlink, Approximating the Optimal Replacement Algorithm,  Proceedings of the ACM International Conference on Computing Frontiers, pp. 313-319, Ischia, Italy, April 2004 
     
  24. P.T. Groen, P. Hamalainen, B.H.H. Juurlink, T. Hamalainen, Accelerating the Secure Remote Password Protocol Using Reconfigurable Hardware,  Proceedings of the ACM International Conference on Computing Frontiers, pp. 471-480, Ischia, Italy, April 2004 
     
  25. P.T. Stathis, D. Cheresiz, S. Vassiliadis, B.H.H. Juurlink, Sparse Matrix Transpose Unit, 18th International Parallel  and Distributed Processing Symposium (IPDPS2004), pp. ??, Santa Fe, New Mexico,  USA, April 2004 
     
  26. G.K. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The MOLEN Processor Prototype, Proceedings of the IEEE  Symposium on Field-Programmable Custom Computing Machines (FCCM'04), Napa, CA, USA, April 2004 
     
  27. Z. Al-Ars, S. Hamdioui, A. J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs,  Proceedings IEEE VLSI Test Symposium, pp. 117-122, Napa, CA, April 2004 
     
  28. T. Niculiu, M. Ciuc, S. D. Cotofana, Hierarchical Models for Intelligent Reconfigurable Simulation,  Proceedings of the 15th IASTED International Conference on Modelling and Simulation (MS 2004), pp. 350-355, Marina del Rey, CA, USA, March 2004 
     
  29. A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J. T. J. van Eijndhoven, Compositional Memory Systems for Data Intensive Applications,  Proceedings of Design, Automation and Test in Europe 2004 (DATE'04), pp.  728-729, Paris, France, February 2004 
     
  30. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, GRAAL - A Development Framework for Embedded Graphics Accelerators,  Proceedings of Design, Automation and Test in Europe (DATE'04), pp. 1366-1367,  Paris, France, February 2004 
     
  31. Z. Al-Ars, A. J. van de Goor, Soft Faults and the Importance of Stresses in Memory Testing,  Proceedings Design, Automation and Test in Europe, pp. 1084-1089, Paris, France, February 2004 
     
  32. K. Bertels, N. Panchanathan, S. Vassiliadis, B Pour Ebrahimi, Centralized Matchmaking for Minimal Agents, Proceedings of the Conference on Parallel and Distributed Computer Systems, pp. 9, November 2004 
     
  33. S. Hamdioui, J.D Reyes, Z. Al-Ars, Evaluation of Intra-Word Faults in Word-Oriented RAMs,  To appear in Proceedings IEEE Asian Test Symposium, Kenting, Taiwan, November 2004 
     
  34. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Effective Computation with Nanodevices: A single Electron Tunneling Case Study, Proceedings of the 2004 International Semiconductor Conference (CAS 2004), pp. 41-50, Sinaia, Romania, October 2004, Invited Paper 
     
  35. E. G. Walters III, C. J. Glossner, M. J. Schulte, Automatic VHDL Model Generation of Parameterized FIR Filters,  Domain Specific Processors : Systems, Architectures, Modeling and Simulation,  pp. 1-17, New York, January 2004 
     
  36. E. Moscu Panainte, K. Bertels, S. Vassiliadis, Compiling for the Molen Programming Paradigm, Proceedings  of the 13th International Conference on Field Programmable Logic and  Applications (FPL'03), pp. 900-910, Lisbon, Portugal, September 2003,  Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 2778 
     
  37. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Single Electron Encoded Logic Memory Elements, proceedings  of 3rd IEEE International Conference on Nanotechnology, pp. 449-452, San  Francisco, USA, September 2003 
     
  38. G.K. Kuzmanov, S. Vassiliadis, Arbitrating Instructions in an ώµ-coded CCM, Proceedings of the 13th International Conference on Field Programmable Logic and Applications  (FPL'03), pp. 81-90, Lisbon, Portugal, September 2003, Springer-Verlag Lecture  Notes in Computer Science (LNCS), vol. 2778 
     
  39. P.T. Stathis, S. Vassiliadis, S. D. Cotofana, D-SAB: A Sparse Matrix Benchmark Suite, Proceedings of 7th International Conference on Parallel Computing Technologies (PaCT 2003), pp. 549-554, Nizhni Novgorod, Russia, September 2003 
     
  40. G.K. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Loading rm-code: Design Considerations, Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and  Simulation, pp. 8-11, Samos, Greece, July 2003 
     
  41. S. Vassiliadis, G. N. Gaydadjiev, K. Bertels, , The Molen Programming Paradigm, Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp.  1-7, Samos, Greece, July 2003 
     
  42. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs,  Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS III), pp. 148-153, Samos, Greece, July 2003 
     
  43. C. J. Glossner, S. Jinturkar, M. Moudgill, E. Hokenek, M. J. Schulte, S. Vassiliadis, Sandbridge Software Tools, Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp.  142-148, Samos, Greece, July 2003 
     
  44. M. Sima, S. Vassiliadis, S. D. Cotofana, J. T. J. van Eijndhoven, Color Space Conversion for MPEG Decoding on FPGA-augmented TriMedia Processor,  Proceedings of the 14th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2003), pp. 250-259, The Hague, The  Netherlands, June 2003 
     
  45. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge,  proceedings of 16th IEEE Symposium on Computer Arithmetic, pp. 245-252, Santiago de Compostela, Spain, June 2003 
     
  46. M. D. Padure, S. D. Cotofana, S. Vassiliadis, CMOS Implementation of Generalized Threshold Functions,  Proceedings of the International Work-conference on Artificial and Natural Neural Networks (IWANN2003), pp. 65-72, Menorca, Spain, June 2003, Vol.  2687/2003 
     
  47. M. D. Padure, S. D. Cotofana, S. Vassiliadis, Design and Experimental Results of a CMOS Flip-Flop Featuring Embedded Threshold Logic,  Proceedings of the IEEE International Symposium on Circuits and Systems, pp.  253-256, Bangkok, Thailand, May 2003, vol. 5 
     
  48. P.T. Stathis, S. Vassiliadis, S. D. Cotofana, A Hierarchical Sparse Matrix Storage Format for Vector Processors,  Proceedings of IPDPS 2003, pp. 61a, Nice, France, April 2003 
     
  49. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Evaluation Methodology for Single Electron Encoded Threshold Logic Gates,  proceedings of the IFIP International Conference on Very Large Scale Integration  of Systems-on-Chip (VLSI-SOC), pp. 258-262, Darmstadt, Germany, December 2003 
     
  50. J Nikara, S. Vassiliadis, FPGA-based Variable Length Decoders, Proceedings of VLSI-SOC 2003, pp. 437-441, Darmstadt, Germany, November 2003 
     
  51. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers,  IEE FPGA Developer's Forum, London, United Kingdom, October 2003, (invited talk) 
     
  52. S. Vassiliadis, J.F. Collard, A. Bode, Parallel Computer Architecture and Instruction level Parallellism,  Proceeedings EURO-PAR 2003 Parallel Processing, pp. 541-542, Berlin, January 2003, Springer Verlag 
  53. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A full adder implementation using SET based linear threshold gates,  Proceedings 9th IEEE International conference on electronics, circuits and  systems - ICECS 2002, pp. 665-669, Dubrovnik, Croatia, September 2002 
     
  54. M. Sima, S. Vassiliadis, S. D. Cotofana, J. T. J. van Eijndhoven, K. A. Vissers, Field-Programmable Custom Computing Machines - A Taxonomy,  Proceedings of the 12th International Conference on Field-Programmable Logic and  Applications (FPL 2002). Reconfigurable Computing Is Going Mainstream, pp.  79-88, Montpellier, France, September 2002, Springer-Verlag, Lecture Notes in  Computer Science (LNCS), Vol. 2438 
     
  55. M. D. Padure, S. D. Cotofana, S. Vassiliadis, C. Dan, M. Bodea, A low-power threshold logic family, 9th IEEE International  Conference on Electronica, Circuits and Systems, pp. 657-660, Croatia, September  2002 
     
  56. S. Wong, S. Vassiliadis, S. D. Cotofana, A Sum of Absolute Differences Implementation in FPGA Hardware,  in Proceedings of the 28th EUROMICRO Conference, pp. 183-188, Dortmund, Germany,  September 2002 
     
  57. J Nikara, S. Vassiliadis, J. Takala, M. Sima, P. Liuha, Parallel multiple-symbol variable-length decoding,  Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 126-131, Freiburg, Germany, September 2002 
     
  58. D. Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Implementation of a streaming execution unit, Proc. DSD  2002; EUROMICRO Symposium on Digital System Design, Architectures, Methods and  Tools, pp. 156-164, Dortmund, Germany, September 2002, Piscataway, NJ. USA: IEEE 
     
  59. D. Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Performance scalability of multimedia instruction set extensions,  Proc. Euro-Par 2002 Parallel processing, pp. 849-861, Padeborn, Germany,  September 2002, Vol. 2400. Lecture notes in computer science. Berlin: Springer. 
     
  60. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Static buffered SET based logic gates, Proceedings of the 2002 2nd IEEE Conference on Nanotechnology, pp. 491-494, August 2002 
     
  61. M. D. Padure, S. D. Cotofana, S. Vassiliadis, High-speed hybrid threshold-Boolean logic counters, 45th International Midwest Symposium on Circuits and Systems, pp. 457-460, Tusla, Oklahoma, USA, August 2002 
     
  62. E. Ogston, S. Vassiliadis, A peer-to-peer agent auction, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part  I, pp. 151-159, Italy, July 2002 
     
  63. S. Wong, S. Vassiliadis, S. D. Cotofana, Future Directions of (Programmable and Reconfigurable) Embedded Processors,  in Proceedings of the SAMOS 2002 Second International Samos Workshop on Systems,  Architectures, Modeling, and Simulation, Samos, Greece, July 2002 
     
  64. M. Sima, E-J Pol, J. T. J. van Eijndhoven, S. D. Cotofana, S. Vassiliadis, Entropy Decoding on TriMedia/CPU64, Proceedings of the 2nd International Workshop on Systems, Architectures, MOdeling and Simulation (SAMOS 2002), Samos, Greece, July 2002, Leiden: SAMOS Initiative 
     
  65. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64,  Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 261-270, Napa Valley, California, USA, April 2002 
     
  66. G.K. Kuzmanov, S. Vassiliadis, ALU Augmentation for MPEG-4 repetitive padding, MPCS'02  Proceedings of the 2002 Euromicro Conference on Massively-Parallel Computing  Systems, Ischia, Italy, April 2002 
     
  67. S. D. Cotofana, P.T. Stathis, S. Vassiliadis, Direct and transposed sparse matrix-vector multiplication,  Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems, MPCS-2002, pp. 1-9, Ischia, Italy, April 2002, The National  Technological University Press, Fort Collins, Colorado, USA. 
     
  68. E. Ogston, S. Vassiliadis, Unstructured agent matchmaking: experiments in timing and fuzzy matching,  Proceedings of the 2002 ACM symposium on applied computing, pp. 300-306, Madrid, Spain, March 2002 
     
  69. D. Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Architectural support for 3D graphics in the complex streamed instruction set, Proceedings of the 14th IASTED International conference on Parallel and distributed computing and systems, PDCS-2002, pp. 536-542, Cambridge, USA, November 2002, Anaheim: ACTA Press, Best paper award in the area of processor architecture, PDCS-2002 
     
  70. G.K. Kuzmanov, S. Vassiliadis, Reconfigurable Repetitive Padding Unit, GLSVLSI '02  Proceedings of the 12th ACM Great Lakes symposium on, pp. 98-103, New York City, NY, USA, January 2002 
     
  71. M. D. Padure, S. D. Cotofana, C. Dan, S. Vassiliadis, M. Bodea, Compact Delay Modeling of Latch-based Threshold Logic Gates, CAS 2002 Proceedings, pp. 317-320, Piscataway, NJ, USA, January 2002, best paper award 
     
  72. B.H.H. Juurlink, D. Cheresiz, S. Vassiliadis, H. A. G. Wijshoff, Implementation and Evaluation of the Complex Streamed Instruction Set,  Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 73-82, Barcelona, September 2001, IEEE Computer Society, Los Alamitos,ISBN: 0-7695-1363-8 
     
  73. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor, Proceedings of the IEEE International Conference on Computer Design (ICCD 2001), pp. 425-430, Austin, Texas, U.S.A., September 2001, Best Paper Award 
     
  74. S. Vassiliadis, S. Wong, S. D. Cotofana, The MOLEN rm-coded Processor, in 11th International  Conference on Field-Programmable Logic and Applications (FPL), Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2147, pp. 275-285, Belfast, UK,  August 2001 
     
  75. D. Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Performance of the complex streamed instruction set on image processing kernels,  Proc. 7th Int. Euro-Par Conference, pp. 678-686, Manchester, UK, August 2001, Springer, Berlin, 2001, ISBN: 3-540-42495-4 
     
  76. G.K. Kuzmanov, S. Vassiliadis, J. T. J. van Eijndhoven, A 2D adressing mode for multimedia applications, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation -  SAMOS, pp. 291-307, Samos, Greece, July 2001, (Lecture notes in computer science, 2268). Berlin: Springer 
     
  77. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, A Reconfigurable Functional Unit for TriMedia/CPU64: A Case Study,  Embedded processor design challenges: Systems, Architectures, Modeling and  Simulation - SAMOS, pp. 224-242, Samos, Greece, July 2001, Springer-Verlag,  Lecture Notes in Computer Science (LNCS), Vol. 2268 
     
  78. S. Wong, S. Vassiliadis, S. D. Cotofana, Microcoded Reconfigurable Embedded Processors: Current Developments,  Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2268, pp. 207-224, Samos, Greece, July 2001 
     
  79. S. Vassiliadis, S. Wong, S. D. Cotofana, Network Processors: Issues and Prospectives, in Proceedings of the International Conference on Parallel and Distributed Processing  Techniques and Applications (PDPTA-2001), pp. 1827-1833, Las Vegas, NV, USA, June 2001 
     
  80. E. Ogston, S. Vassiliadis, Matchmaking among minimal agents without a facilitator,  Proceedings. 5th International Conference on Autonomous Agents, pp. 608-615,  Montreal, Canada, May 2001 
     
  81. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A linear threshold gate implementation in single electron technology,  Proceedings. IEEE Computer Society Workshop on VLSI 2001: Emerging Technologies for VLSI Systems, pp. 93-98, Orlando, USA, April 2001 
     
  82. M. Sima, S. D. Cotofana, J. T. J. van Eijndhoven, S. Vassiliadis, K. A. Vissers, An 8x8 IDCT Implementation on an FPGA-augmented TriMedia,  Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2001), Rohnert Park, California, USA, April 2001 
     
  83. S. Wong, S. D. Cotofana, S. Vassiliadis, Coarse Reconfigurable Multimedia Unit Extension,  Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing  (PDP 2001), pp. 235-242, Mantova, Italy, February 2001 
     
  84. P.T. Stathis, S. D. Cotofana, S. Vassiliadis, Sparse Matrix Vector Multiplication Evaluation Using the BBCS scheme,  Proc. of 8th Panhellenic Conference on Informatics, pp. 40-49, Nicosia, Cyprus, November 2001, ISBN: 960-14-0458-9 
     
  85. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Achieving fanout capabilities in single electron encoded logic networks,  Proceedings. Vol. 2. 6th International Conference on Solid-State and Integrated Circuit Technology, pp. 1383-1386, Shanghai, China, October 2001 
     
  86. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Digital to analog conversion performed in single electron technology,  proceedings. 1st IEEE Conference on Nanotechnology, pp. 105-110, Maui, USA, October 2001 
     
  87. M. D. Padure, S. D. Cotofana, C. Dan, M. Bodea, S. Vassiliadis, A new latch-based threshold logic family, Proceedings of International Semiconductor Conference CAS 2001, pp. 531 -534, Sinaia, Romania,  October 2001 
     
  88. E. Ogston, S. Vassiliadis, Local distributed agent matchmaking, pp. 67-79, Berlin, January 2001, ISBN: 3-540-42524-1, cat. f, Projectcode: ET01-05 
     
  89. S. Vassiliadis, G.K. Kuzmanov, S. Wong, MPEG-4 and the New Multimedia Architectural Challenges, in Proceedings of the 15th International conference on Systems for automation of  engineering and research (SAER-2001), pp. 24-32, Sofia, Bulgaria, January 2001 
     
  90. "The Artemis Architecture Workbench" A.D.Pimental, P. van der Volf,E.F.A.Deprettere, L.O.Hertzberger, J.T.J. van Eijndhoven, S.Vassiliadis, Proceedings of the First PROGRESS workshop, Utrecht, The Netherlands, October 13, 2000, pp.53-62.
     
  91. "A Taxonomy of Custom Computing Machines" M.Sima, S.Vassiliadis, S.Cotofana, J.van Eijndhoven, K.Vissers, Proceedings of the First PROGRESS workshop, Utrecht, The Netherlands, October 13, 2000, pp.71-78.
     
  92. S. Vassiliadis, B.H.H. Juurlink, E. A. Hakkennes, Complex streamed instructions: introduction and initial evaluation,  Proc. 26th Euromicro Conference, vol 1, pp. 400-408, Maastricht, Netherlands, September 2000, IEEE Computer Society, Los Alamitos, 2000. ISBN: 0-7695-0780-8 
     
  93. G. G. Pechanek, S. Vassiliadis, The ManArray (TM) embedded processor architecture, Proceedings  of the 26th Euromicro Conference, pp. 348 - 355 vol.1, Maastricht , Netherlands, September 2000, IEEE Computer Society 
     
  94. S. D. Cotofana, B.H.H. Juurlink, S. Vassiliadis, Counter Based Superscalar Instruction Issuing, Proceedings  of the 26th Euromicro Conference, vol. 1, pp. 307-315, Maastricht, The  Netherlands, September 2000 
     
  95. M. Stanca, H. Corporaal, S. D. Cotofana, S. Vassiliadis, Hashed Addressed Caches for Embedded Pointer Based Codes,  Proc. 6th Euro-Par 2000 Conference, pp. 278-284, Munich, Germany, August 2000,  LNCS 1900, Springer, 2000 
     
  96. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, BBCS based sparse matrix-vector multiplication: initial evaluation,  Proc. 16th IMACS World Congress on Scientific Computation, Applied Mathematics and Simulation, pp. 1-6, Lausanne, Switzerland, August 2000, ISBN: 3-9522075-1-9 
     
  97. S. Wong, S. D. Cotofana, S. Vassiliadis, Multimedia Enhanced General-Purpose Processors, Proceedings  of the International Conference on Multimedia and Expo, pp. 1-4, New York City, NY, USA, July 2000 
     
  98. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, Block Based Compression Storage Expected Performance, Proc.  14th Int. Conf. on High Performance Computing Systems and Applications (HPC  2000), pp. 389-406, Victoria, Canada, June 2000, Kluwer Academic Publishers, ISBN: 0-7923-7617-X 
     
  99. S. Wong, S. D. Cotofana, S. Vassiliadis, General-Purpose Processor Huffman Encoding Extension,  Proceedings of the International Conference on Information Technology: Coding  and Computing (ITCC 2000), pp. 158-163, Las Vegas, Nevada, March 2000 
     
  100. A. Berlea, S. D. Cotofana, I. Athanasiu, C. J. Glossner, S. Vassiliadis, Garbage collection for the Delft Java Processor,  Proceedings of the 8th IASTED International Conference on Applied Informatics (AI-2000), pp. 232-238, Innsbruck, Austria, February 2000 
     
  101. M. Stanca, H. Corporaal, S. D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction,  Proc. of IASTED Int. Conf on Applied Informatics 2000, Inssbruck, Austria,  February 2000, IASTED, Annaheim, 2000 
     
  102. F.J. Gutierrez, E. Varvarigos, S. Vassiliadis, Multi-cost routing in Max-Min fair share networks,  Proceedings. Vol. 2. 38th Annual Allerton Conference on Communication, Control  and Computing, pp. 1294-1304, Monticello, Illinois, October 2000, cat. c,  Projectcode: ET01-05 
     
  103. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, Vector ISA Extension for Sprase Matrix-Vector Multiplication,  Proceedings of EuroPar'99 Parallel Processing, pp. 708-715, Toulouse, France,  September 1999 
     
  104. C. J. Glossner, S. Vassiliadis, Delft-Java Dynamic Translation,  proceedings. Vol. 2. 25th Euromicro Conference, pp. 57-61, Milan, Italy, September 1999, IEEE, S.l., 1999, ISBN: 1089-6503 
     
  105. E. A. Hakkennes, S. Vassiliadis, Hardwired Paeth codec for portable network graphics (PNG),  Euromicro 99, pp. 318-325, Milan, Italy, September 1999 
     
  106. G. G. Pechanek, S. Vassiliadis, N. Pitsianis, ManArray Processor Interconnection Network: An Introduction,  Proceedings of the 5th International EuroPar Conference on Parallel Processing,  pp. 761-765, September 1999, (Lecture Notes in Computer Science 1685) 
     
  107. M. D. Padure, C. Dan, S. D. Cotofana, M. Bodea, S. Vassiliadis, Capacitive Threshold Logic: A Design Perspective, 22nd International Semiconductor Conference CAS 1999, pp. 81-84, October 1999 
     
  108. T. L. Jeremiah, S. Vassiliadis, B. Blaner, Superscalar branch instruction processor,  proceedings. Vol. 2. 12th International Conference on Control Systems and  Computer Science, pp. 163-168, Bucharest, January 1999, ISBN: 973-96609-5 
     
  109. S. Jinturkar, J. Thilo, C. J. Glossner, P. G. D'Arcy, S. Vassiliadis, Profile Directed Compilation in DSP Applications,  Proceedings of the International Conference on Signal Processing Applications  and technology (ICSPAT'98), September 1998 
     
  110. S. D. Cotofana, S. Vassiliadis, On the Design Complexity of the Issue Logic of Superscalar Machines,  Proc. of 24th EUROMICRO Conf., pp. 277-284, Vasteras, Sweden, August 1998, IEEE Computer Society, ISBN: 0-8186-8646-4 
     
  111. C. J. Glossner, S. Vassiliadis, Delft-JAVA Link Translation Buffer, Euromicro 98, pp.  221-228, Vasteras, Sweden, August 1998, ISBN: 0-8186-8646-4 
     
  112. S. Vassiliadis, E. A. Hakkennes, S. Wong, G. G. Pechanek, The Sum-of-Absolute-Difference Motion Estimation Accelerator,  in Proceedings of the 24th Euromicro Conference, pp. 559-566, Vasteras, Sweden, August 1998 
     
  113. A. Stokman, S. D. Cotofana, S. Vassiliadis, A Versatile Threshold Logic Gate, 1998 International Semiconductor Conference, pp. 163-166, Sinaia, Romania, July 1998, ISBN: 0-7803-4432-4, best paper award 
     
  114. S. D. Cotofana, S. Vassiliadis, On Serial Multiplication with Neural Networks, Proc. of NEURAP '98, pp. 43-50, Marseilles, France, March 1998, IUSPIM, Marseille 
     
  115. C. J. Glossner, J. Thilo, S. Vassiliadis, Java Signal Processing: FFT's with Bytecodes, Proceedings  of ACM 1998 Workshop on Java for High-Performance Network Computing, pp. 239-243, Palo Alto, California, USA, February 1998
     
  116. C. J. Glossner, S. Vassiliadis, The Delft-Java Engine: An Introduction, Lecture Notes In Computer Science, Third International Euro-Par Conference (Euro-Par'97 Parallel  Processing), pp. 766-770, Passau, Germany, August 1997 
     
  117. S. D. Cotofana, S. Vassiliadis, "Low Weight and Fan-In Neural Networks for Basic Arithmetic Operations,  Proc. of 15th IMACS World Congress on Scientific Computation, Modeling and Applied Mathematics, pp. 227-232, Berlin, August 1997, Wissenschaft & Technik  Verlag 
     
  118. E. A. Hakkennes, S. Vassiliadis, S. D. Cotofana, Fast Computation of Compound Expressions in Two's Complement Notation,  Proceedings of the 15th IMACS World Congress on Scientific Computation, Modeling  and Applied Mathematics, pp. 689-694, Berlin, August 1997 
     
  119. S. D. Cotofana, S. Vassiliadis, Signed Digit Counters with Neural Networks, Proc.  Neurap'97, pp. 55-62, Marseille, March 1997, Ecole d'Ingenieurs de l'Universite de Marceille 
  120. S. D. Cotofana, S. Vassiliadis, Serial Binary Addition with Polynomially Bounded Weights,  Proceedings of the International Conference on Artificial Neural Networks (ICANN  '96), pp. 741-746, Bochum, Germany, July 1996 
     
  121. V. C. Aikens, J. G. Delgado-Frias, S. M. Barber, G. G. Pechanek, S. Vassiliadis, A Neuro-Emulator with Learning and Virtual Emulation Capabilities,  IEEE Int'l Conference on Neural Networks, pp. 1355-1360, Washington, DC, June 1996 
     
  122. J. E. Phillips, S. Vassiliadis, High-Performance Dividers with Multiply-Add, Proceedings  Second Int'l Conf Massively Parallel Computing Systems, pp. 406-413, Ischia, Italy, May 1996 
     
  123. C. J. Glossner, G. G. Pechanek, S. Vassiliadis, J. Landon, High-Performance Parallel FFT Algorithms on M.f.a.s.t. using Tensor Algebra,  Proceedings of the Signal Processing Applications Conference DSP-X'96, pp.  529-536, San-Jose, CA, March 1996 
     
  124. W. Cnossen, S. Vassiliadis, Deadlock-free Virtual Channel Assignment in the Clustered Torus,  Proceedings of the Second International Conference on Massively Parallel  Computing Systems (MPCS 96), pp. 72-78, Ischia, Italy, March 1996 
     
  125. S. D. Cotofana, S. Vassiliadis, Periodic Symmetric Functions with Feed-Forward Neural Networks,  Proceedings of the Conference on Neural Networks and Their Applications (NEURAP  ''95/96), pp. 215-221, Marseille, France, March 1996 
     
  126. Y. Sazeides, S. Vassiliadis, J. E. Smith, The Performance Potential of Data Dependence Speculation & Collapsing,  Proc. 29th Symp. On Microarchitecture MICRO-29, pp. 238-249, Paris, France, December 1996 
     
  127. S. D. Cotofana, S. Vassiliadis, 2-1 Redundant Addition with Threshold Logic, Proc. of the 13th ASILOMAR Conf. on Signals, Systems & Computers, pp. 889-893, Pacific Grove, CA, November 1996, IEEE Computer Society 
     
  128. S. Vassiliadis, S. D. Cotofana, 7| 2counters and multiplication with threshold logic,  Record of the Thirtieth Asilomar Conference on Signals, Systems and Computers, pp. 192 - 196 vol.1, Pacific Grove, CA , USA, November 1996 
     
  129. M. Moudgill, S. Vassiliadis, Mechanisms for Specifying Static Speculation, Proceedings  of the 21st Euromicro Conference, pp. 293-300, Como, Italy, September 1995 
     
  130. B. Blaner, S. Vassiliadis, T. L. Jeremiah, A Branch Instruction Processor for SCISM Organizations,  Proceedings of the 21st Euromicro Conference, Design of Hardware/Software Systems, pp. 285-292, Como, Italy, September 1995, ISBN 0-8186-7127-0 
     
  131. S. Vassiliadis, J. Hoekstra, S. D. Cotofana, Block Save Addition with Telescopic Sums, Proceedings of EUROMICRO '95 Conference, pp. 701-707, Como, Italy, September 1995 
     
  132. K. Bertels, L. Neuberg, S. Vassiliadis, G. G. Pechanek, XOR and Backpropagation Learning: In and Out of the Chaos?,  Proceedings ESANN '95 European Symposium on Artificial Neural Networks, pp. 69-74, Brussel, Belgium, April 1995 
     
  133. S. Vassiliadis, S. D. Cotofana, J. Hoekstra, Block Save Addition with Threshold Logic, Conference Record  of the Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, pp.  575-579, Los Alamitos, CA, October 1995 
     
  134. G. G. Pechanek, M. Stojancic, S. Vassiliadis, C. J. Glossner, MFAST: a single chip highly parallel image processing architecture,  International Conference on Image Processing, pp. 69 - 72 vol.1, Washington, DC , USA, October 1995 
     
  135. V. C. Aikens, S. M. Barber, J. G. Delgado-Frias, G. G. Pechanek, S. Vassiliadis, A Neuro-Architecture with Embedded Learning,  Seventh IASTED/ISMM International Conference, Parallel and Distributed Computing  and Systems, pp. 103-106, Washington D.C, October 1995, ISBN 0-88986-228-1 
     
  136. ``Tensor Product FFT's on M.f.a.s.t.: A Highly Parallel Single Chip DSP'' , G.G. Pechanek, C.J. Glosner, Z. Li, C.H. Moller, S. Vassiliadis, IEEE DSP 95, Conf. Proc., October 1995, Paris, France.
     
  137. S. Vassiliadis, K. Bertels, G. G. Pechanek, Feedforward ANN for 2-1 Fixed Point ALUs, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, pp. 156-162, Los Alamitos, CA, September 1994 
     
  138. M. Zhang, J. G. Delgado-Frias, S. Vassiliadis, Table Driven Newton Scheme for High Precision Logarithm Generation,  IEE Proceedings Computers and Digital Techniques, pp. 281-292, McCaw Cellular Commun. Inc., Kirkland, WA, September 1994, Vol.: 141, Issue: 5 
     
  139. J. G. Delgado-Frias, G. G. Pechanek, S. Vassiliadis, H. Ding, W. Lin, Organization and Implementation of a Highly Pipelined Neuroemulator,  Proceedings of the 14th IMACS World Congress on Computation and Applied Mathematics, pp. 661-664, Atlanta, USA, July 1994 
     
  140. W. Lin, J. G. Delgado-Frias, G. G. Pechanek, S. Vassiliadis, Impact of Energy Function on a Neural Network Model for Optimization Problems,  Proceedings of the 1994 IEEE International Conference on Neural Networks, pp. 4518-4523, Orlando, June 1994, USA 
     
  141. W. Lin, J. G. Delgado-Frias, S. Vassiliadis, G. G. Pechanek, An Investigation of the Precision Impact on the Hopfield-Tank Neural Network Model for the TSP,  Proceedings of the 1994 IEEE International Conference on Neural Networks, pp.  4523-4528, Orlando, USA, June 1994 
     
  142. S. Vassiliadis, G. Triantafyllos, G. G. Pechanek, A Method for Computing the Most Typical Fuzzy Expected Value,  IEEE World Congress on Computational Intelligence., Proceedings of the Third IEEE Conference on Fuzzy Systems, pp. 2040 -2045, Orlando, June 1994, vol.3 
     
  143. S. Vassiliadis, K. Bertels, G. G. Pechanek, O(n) Depth-2 Binary Addition with Feedforward Neural Nets,  Proc. of 1994 Int. Conference on Neural Networks, pp. 1381-1385, Orlando, USA,  June 1994, ISBN: 0-7803-1901-X 
     
  144. G. G. Pechanek, S. Vassiliadis, J. G. Delgado-Frias, G. Triantafyllos, Scalable completely connected digital neural networks, IEEE World Congress on CComputational Intelligence, IEEE International Conference,  pp. 2078 - 2083 vol.4, Orlando, FL, USA, June 1994 
     
  145. G. G. Pechanek, S. Vassiliadis, J. G. Delgado-Frias, The folded axon/dendrite tree neuron model, Neural Networks, IEEE World Congress on Computational Intelligence, IEEE International  Conference, pp. 1397 - 1402 vol.3, Orlando, FL, USA, June 1994 
     
  146. G. Triantafyllos, S. Vassiliadis, Experiments with Error Prediction Models,  Proc. Seventh International Software Quality Week, May 1994, Software Research  Institute, San Francisco, 1994 
     
  147. D. H. Summerville, J. G. Delgado-Frias, S. Vassiliadis, A High Performance Pattern Associative Oblivious Router for Tree Topologies,  Proc. 8th Int. Parallel Processing Symposium, pp. 541-545, Cancun, Mexico, April  1994, ISBN 0-8186-5602-6, IEEE Computer Society Press 
     
  148. J. G. Delgado-Frias, S. Vassiliadis, H.D. Johnson, D. H. Summerville, D. M. Green, A. de Luca, A Processor for MIMD Machine Organizations,  IEEE Mexicon 94 International Conference on Electrical, Electronics, and  Computer Engineering, pp. 94-112, Puebla, Mexico, February 1994 
     
  149. W. Lin, J. G. Delgado-Frias, D.C. Gause, S. Vassiliadis, Solving the Traveling Salesman Problem using a Hybrid Genetic Algorithm Approach,  Proceedings of the Artificial Neural Networks in Engineering (ANNIE '94)  Conference, pp. 1069-1074, St. Louis, USA, November 1994 
     
  150. J. Park, B. O'Krafka, S. Vassiliadis, J. Delgado-Frias, Design and Evaluation of a DAMQ Multiprocessor Network Switch with Self-Compacting Buffers, IEEE Supercomputing 94, The conference on  High Performance Computing and Communications, Conf. Proc. pp: 713-722, November 1994, Washington, DC.
     
  151. S. Vassiliadis, K. Bertels, O(n) Depth-3 Binary Addition, Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, pp.  536-539, Pacific Grove, CA, October 1994, vol.1
     
  152. M. Moudgill, K. Pingali, S. Vassiliadis, Register Renaming and Dynamic Speculation: An  Alternative Approach, ACM/IEEE The 26th Annual International Symposium on Microarchitecture (MICRO 26) Conf. Proc.  pp. 202-213, December 1993, Austin, Texas.
     
  153. H. Johnson, J. Delgado-Frias, S. Vassiliadis, D. M. Green, A Petri Net Technique for Accessing Performance of Multiprocessor Architectures, Performance Evaluation of Parallel Systems Conf. Proc. pp. 43-50, November 1993, University of Warwick, Coventry, United Kingdom.
     
  154. G. Pechanek, S.  Vassiliadis, J. Delgado-Frias, Multiple-Fold Clustered Processor Mesh Array, IEEE Fifth NASA Symposium on VLSI Design, Conf.  Proc. pp. 8.4.1-8.4.11, November 1993, Albuquerque, New Mexico.
     
  155. S. Vassiliadis, J. Delgado-Frias, M. Zhang, First Order Piece-Wise Sigmoid Generators, Artificial Neural Networks in Engineering(ANNIE 93), Conf. Proc. pp. 77-82, November 1993, St. Louis, Missouri.
     
  156. G. Pechanek, J. Delgado-Frias, S. Vassiliadis, A Massively Parallel Diagonal-Fold Mesh Array Processors, EURO-Micro and IEEE, International Conference  on Application Specific Array Processors, Conf. Proc. pp. 140-143, October 1993,  Venice, Italy, also appeared as a refereed IBM Technical Report TR 01.C420, pp. 24, September 1992.
     
  157. W. Lin, J. Delgado-Frias, S. Vassiliadis, G. Pechanek, Machine and Bit Precision on the Hopfield Neural Network Model for the  TSP, IEEE International Joint Conference on Neural Networks (IJCNN), Conf. Proc. pp. 1516-1519, October  1993, Nagoya, Japan.
     
  158. S. Barber, J. Delgado-Frias, S. Vassiliadis, G. Pechanek, SPIN-L: Sequential Pipeline Neuroemulator with Learning Capabilities, IEEE International Joint Conference on Neural Networks (IJCNN), Conf. Proc. pp. 1927-1930, October  1993, Nagoya, Japan.
     
  159. M. Zhang, S. Vassiliadis, J. Delgado-Frias, High Performance with Low Implementation Cost Sigmoid Generators, IEEE International Joint Conference on Neural Networks (IJCNN), Conf. Proc. pp. 1931-1934, October 1993, Nagoya, Japan.
     
  160. J. Park, S.  Vassiliadis, J. G. Delgado-Frias, Router Architecture for Oblivious Routing Algorithms, Proceedings of Parallel Computing Technologies  PaCT-93, August 1993, Obnisk, Russia.
     
  161. W.C. Wu, S.  Vassiliadis, T.Y. Chung, Performance Analysis of Multi-Channel ARQ Protocols, IEEE 36th Midwest Symposium on Computers and Systems,  Conf. Proc. pp. 1328-1331, August 1993, Detroit, Michigan.
     
  162. G. Triantafyllos,  S. Vassiliadis, J. Delgado-Frias, Defects and System Simulation: An Empirical Analysis, SCS European Simulation Multiconference, Conf. Proc. pp. 75-79, June 1993, Lyon, France.
     
  163. G. Triantafyllos, S. Vassiliadis, J. Delgado-Frias, Analyzing Error-Prone Microcode Modules, Int'l Test and Evaluation Assoc., 10th  International Conference on Testing Software, Conf. Proc. pp. 101-110, June 1993, Washington, D.C..
     
  164. S. Vassiliadis, B. Blaner, R. Eickemeyer, J. Phillips, N. Malik, In-Cache Pre-Processing and Decode Mechanisms for Fine Grain Parallelism in SCISM, IEEE Phoenix Conference on Computer and Communication, Conf. Proc. pp. 91-97, March  1993, Phoenix, Arizona. Invited Paper.
     
  165. N. Malik, R. Eickemeyer, S. Vassiliadis, Architectural Effects on Dual Instruction Issue with Interlock Collapsing ALUs, IEEE Phoenix Conference on Computer and Communication, Conf. Proc. pp. 42-48, March 1993, Phoenix, Arizona.
     
  166. N. Malik, S. Vassiliadis, J. Phillips, Execution Dependencies and Their Resolution in Fine Grain Parallel Machines, IEEE Phoenix Conference on Computer and Communication, Conf. Proc. pp. 86-90, March 1993, Phoenix, Arizona. Invited Paper.
     
  167. N. Malik, R. Eickemeyer, S. Vassiliadis, Interlock Collapsing ALU for Increasing Instruction level Parallelism, ACM/IEEE The 25th Annual International Symposium on Microarchitecture (MICRO 25), Conf. Proc. pp. 149-157, December 1992, Portland, Oregon, Honorable Mention Best Paper Award.
     
  168. N. Malik, R. Eickemeyer, S. Vassiliadis, Execution Interlock Collapsing Under Restricted Memory Models, Seventh International Symposium on Computer and Informational Sciences, Conf. Proc. pp. 181-187, November 1992, Antalia, Turkey.
     
  169. T. Ryan, J. G. Delgado-Frias,  S. Vassiliadis, G. G. Pechanek, D. Green, A Dataflow Approach for Neural Networks, Third International Workshop on VLSI for Artificial Intelligence and Neural Networks, September 1992, University of Oxford, Oxford, England, pp. 151-158, VLSI for Neural Networks and Artificial  Intelligence, J. Delgado-Frias and W. Moore(Editors) Plenum Press,(New York),  1994.
     
  170. J. G. Delgado-Frias, S. Vassiliadis, G.  G. Pechanek, W. Lin, S. Barber, H. Ding, A VLSI Pipelined Neuroemulator, Proceedings of Third International Workshop on VLSI for Artificial Intelligence and Neural Networks, September  1992, University of Oxford, Oxford, England, pp.71-80, VLSI for Neural Networks  and Artificial Intelligence, J. Delgado-Frias and W. Moore (Editors) Plenum  Press, (New York), 1994.
     
  171. G. G. Pechanek, S. Vassiliadis, J. G. Delgado-Frias, Review of Digital Emulators Using Tree Accumulation and Communication  Structures, ITC Conference on Neural Networks, Conf. Proc. pp. 160-164, May 1992, East-Fishkill, New York.
     
  172. S. Vassiliadis, G. G.  Pechanek, J. G. Delgado-Frias, SPIN: A Sequential Pipelined Neuroemulator (also in the International  Journal on Artificial Intelligence Tools, March 1993), IEEE third International Conference on Tools for Artificial Intelligence Conf. Proc. pp.74-81, November 1991, San Jose, California.
     
  173. G. G. Pechanek, S. Vassiliadis, J. G. Delgado-Frias, Neurocomputer Architecture Survey, IEEE S.T.T. Conference, Conf. Proc. pp. 101-108, October 1991, Binghamton, NY.
     
  174. G. Triantafyllos, S. Vassiliadis, W. Kobrosly, Error Prediction Models in Software Engineering, IEEE S.T.T. Conference, Conf. Proc. pp. 61-69, October 1991, Binghamton, NY.
     
  175. S. Vassiliadis,  E. Schwarz, Controlling Unit for a Floating Point Hardwired Engine, Proceedings of IFIP Third International Workshop on W.S.I, June 1989,  Como, Italy, pp. 343-351, Wafer Scale Integration, III, M. Sami and F. Distante (Editors), Elsevier Science Publishers B.V., (North-Holland), IFIP 1990.
     
  176. S. Vassiliadis, E. Schwarz, M. Putrino, Parity Predict for 34-bit Adders with Selection, IEEE S.T.T. Conference, Conf. Proc. pp. 52-59, October 1988, Binghamton, NY.
     
  177. W. Kobrosly, S.  Vassiliadis, A Survey Of Software Functional Testing Techniques, IEEE S.T.T. Conference, Conf. Proc. pp. 127-134, October 1988, Binghamton, NY.
     
  178. S. Vassiliadis, M. Putrino, E. Schwarz, Unified Multi-bit Overlapped Scanning Multiplier Algorithm, IEEE S.T.T. Conference, Conf. Proc. pp.  68-75, October 1988, Binghamton, NY.
     
  179. S. Vassiliadis, E. Schwarz, M. Putrino, Quasi-Universal VLSI Multiplier with Signed Digit Arithmetic, IEEE S.T.T. Conference, Conf. Proc. pp.  77-91, April 1987, Binghamton, NY.
     
  180. E. Schwarz, S. Vassiliadis, M. Putrino,Direct Computation of the Polynomial Expression AX^2 + BX + C, IEEE S.T.T. Conference, Conf. Proc. pp. 101-111, April 1987, Binghamton, NY.

 

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