Journal Publications

1. Z. Al-Ars, S. Hamdioui, A.J. van de Goor and S. Al-Harbi, ``Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs,'' in IEEE Trans. on Computer-Aided Design (TCAD'06), vol. 25, no. 12, December 2006, pp. 2989-2996.
   Get paper here.
   
   
2. S. Hamdioui, Z. Al-Ars and A.J. van de Goor, ``Opens and Delay Faults in CMOS RAM Address Decoders,'' in IEEE Trans. on Computers (TC'06), vol. 55, no. 12, December 2006, pp. 1630-1639.
   Get paper here.
   
   
3. Z. Al-Ars and A.J. van de Goor, ``Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs,'' in IEEE Trans. on Computers (TC'03), vol. 52, no. 3, March 2003, pp. 293-309.
   Get paper here.
   
   
4. S. Hamdioui, Z. Al-Ars and A.J. van de Goor, ``Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests,'' in Journal of Electronic Testing: Theory and Applications (JETTA'03), April 2003, pp. 195-205.
   Get paper here.
   
   
5. Z. Al-Ars and A.J. van de Goor, ``Test Generation and Optimization for DRAM Cell Defects Using Electrical Simulation,'' in IEEE Trans. on Computer-Aided Design (TCAD'03), vol. 22, no. 10, October 2003, pp. 1371-1384.
   Get paper here.
   
   
6. S. Hamdioui, Z. Al-Ars, A.J. van de Goor and M. Rodgers, ``Linked Faults in Random-Access-Memories: Concept, Fault Models, Test Algorithms and Industrial Results,'' in IEEE Trans. on Computer-Aided Design (TCAD'04), vol. 23, no. 5, May 2004, pp. 737-757.
   Get paper here.
   
   

Conference Publications

7. L. Hasan and Z. Al-Ars, ``Performance Improvement of The Smith-Waterman ---A Local Sequence Alignment Algorithm,'' in Proc. ProRISC Workshop (18th ProRISC'07), Veldhoven, the Netherlands, November 29-30, 2007, pp. ???-???.
   Get paper here.
   
   
8. Z. Al-Ars and S. Kootkar, ``Design and Implementation of Reliable Wireless Sensor Networks---A Case Study in Commuter Trains,'' in Proc. ProRISC Workshop (18th ProRISC'07), Veldhoven, the Netherlands, November 29-30, 2007, pp. ???-???.
   Get paper here.
   
   
9. L. Hasan, Z. Al-Ars and S. Vassiliadis, ``Hardware Acceleration of Sequence Alignment Algorithms---An Overview,'' in Proc. IEEE International Conf. on Design and Technology of Integrated Systems in Nanoscale Era (2st DTIS'07), Rabat, Morocco, September 02-05, 2007, pp. ???-???.
   Get paper here.
   
   
10. Z. Al-Ars and S. Hamdioui, ``Automatic Analysis of Memory Faulty Behavior in Defective Memories,'' in Proc. IEEE International Conf. on Design and Technology of Integrated Systems in Nanoscale Era (2st DTIS'07), Rabat, Morocco, September 02-05, 2007, pp. ???-???.
    Get paper here.
    
    
11. S. Hamdioui, Z. Al-Ars, J. Jimenez and J. Calero, ``PPM Reduction on Embedded Memories in System on Chip,'' in Proc. IEEE European Test Symp. (12th ETS'07), Freiburg, Germany, May 20-24, 2007, pp. 85-90.
    Get paper here.
    
    
12. Z. Al-Ars, S. Hamdioui and G.N. Gaydadjiev, ``Optimizing Test Length for Soft Faults in DRAM Devices,'' in Proc. IEEE VLSI Test Symposium (25th VTS'07), Berkeley, California, May 6-10, 2007, pp. 59-66.
    Get paper here.
    
    
13. Z. Al-Ars, S. Hamdioui and G.N. Gaydadjiev, ''Manifestation of Precharge Faults in High Speed DRAM Devices,'' in Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (10th DDECS'07), Kraków, Poland, April 11-13, 2007.
    Get paper here.
    
    
14. B. Tunçe, Z. Al-Ars, E. Akar, J. Beintema and S. Sariyildiz, ``DesignMap: Capturing Design Knowledge in Architectural Practice,'' in Proc. Joint International Conf. on Construction Culture, Innovation and Management (CCIM'06), Dubai, UAE, November 26-29, 2006, ISBN: 0 947974 53 9, pp. 90-91.
    Get paper here.
    
    
15. S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev and J.D. Reyes, ``Comparison of Static and Dynamic Faults in 65nm Memory Technology,'' in Proc. IEEE International Design and Test Workshop (1st IDT'06), Dubai, UAE, November 19-20, 2006.
    Get paper here.
    
    
16. Z. Al-Ars, S. Hamdioui, G.N. Gaydadjiev, ``Using Linear Tests for Transient Faults in DRAMs,'' in Proc. IEEE International Design and Test Workshop (1st IDT'06), Dubai, UAE, November 19-20, 2006.
    Get paper here.
    
    
17. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G.N. Gaydadjiev and J. Vollrath, ``DRAM-Specific Space of Memory Tests,'' in Proc. IEEE International Test Conf. (37th ITC'06), Santa Clara, California, October 24-26, 2006.
    Get paper here.
    
    
18. S. Hamdioui, Z. Al-Ars, L. Mhamdi, G.N. Gaydadjiev and S. Vassiliadis, ``Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies,'' in Proc. IEEE International Conf. on Design and Test of Integrated Systems in Nanoscale Technology (1st DTIS'06), Tunis, Tunisia, September 05-07, 2006, pp. 216-221.
    Get paper here.
    
    
19. S. Hamdioui, Z. Al-Ars, G.N. Gaydadjiev and J.D. Reyes, ``Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies,'' in Proc. IEEE European Test Symposium Digest of Papers (11th ETS'06), Southampton, UK, May 21-25, 2006.
    Get paper here.
    
    
20. Z. Al-Ars, S. Hamdioui, G. Mueller and J. Vollrath, ``Bitline-Coupled Precharge Faults and Their Detection in Memory Devices,'' in Proc. IEEE European Test Symposium Digest of Papers (11th ETS'06), Southampton, UK, May 21-25, 2006.
    Get paper here.
    
    
21. Z. Al-Ars, S. Hamdioui and A.J. van de Goor, ``Space of DRAM Fault Models and Corresponding Testing,'' in Proc. Design, Automation and Test in Europe (9th DATE'06), Munich, Germany, March 6-10, 2006, pp. 1252-1257.
    Get paper here.
    
    
22. Z. Al-Ars, S. Hamdioui and J. Vollrath, ``Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach,'' in Proc. Asian Test Symp. (14th ATS'05), Kolkata, India, December 18-21, 2005, pp. 434-439.
    Get paper here.
    
    
23. S. Hamdioui, Z. Al-Ars, A.J. van de Goor and R. Wadsworth, ``Impact of Stresses on the Fault Coverage of Memory Tests,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (13th IEEE MTDT'05), Taipei, Taiwan, August 3-5, 2005, pp. 103-108.
    Get paper here.
    
    
24. Z. Al-Ars, S. Hamdioui, G. Mueller and A.J. van de Goor, ``Framework for Fault Analysis and Test Generation in DRAMs,'' in Proc. Design, Automation and Test in Europe (8th DATE'05), Munich, Germany, March 7-11, 2005, pp. 1020-1021.
    Get paper here.
    
    
25. S. Hamdioui, J.D. Reyes and Z. Al-Ars, ``Evaluation of Intra-Word Faults in Word-Oriented RAMs,'' in Proc. Asian Test Symp. (13th ATS'04), Kenting, Taiwan, November 15-17, 2004, pp. 283-288.
    Get paper here.
    
    
26. A.J. van de Goor, S. Hamdioui and Z. Al-Ars, ``The Effectiveness of Scan Test and Its New Variants,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (12th IEEE MTDT'04), San Jose, California, August 9-11, 2004, pp. 26-31.
    Get paper here.
    
    
27. Z. Al-Ars, M. Herzog, I. Schanstra and A.J. van de Goor, ``Influence of Bit Line Twisting on the Faulty Behavior of DRAMs,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (12th IEEE MTDT'04), San Jose, California, August 9-10, 2004, pp. 32-37.
    Get paper here.
    
    
28. A.J. van de Goor, S. Hamdioui and Z. Al-Ars, ``Tests for Address Decoder Delay Faults in RAMs due to Inter-Gate Opens,'' in Proc. European Test Symp. (9th IEEE ETS'04), Corsica, France, May 23-26, 2004, pp. 146-151.
    Get paper here.
    
    
29. Z. Al-Ars, S. Hamdioui and A.J. van de Goor, ``Effects of Bit Line Coupling on the Faulty Behavior of DRAMs,'' in Proc. IEEE VLSI Test Symp. (22nd IEEE VTS'04), Napa, California, April 25-29, 2004, pp. 117-122.
    Get paper here.
    
    
30. Z. Al-Ars and A.J. van de Goor, ``Soft Faults and the Importance of Stresses in Memory Testing,'' in Proc. Design, Automation and Test in Europe (7th DATE'04), Paris, France, February 16-20, 2004, pp. 1084-1089.
    Get paper here.
    
    
31. S. Hamdioui, Z. Al-Ars, A.J. van de Goor and M. Rodgers, ``March SL: A Test for All Static Linked Memory Faults,'' in Proc. Asian Test Symp. (12th ATS'03), Xian, China, November 17-19, 2003, pp. 372-377.
    Get paper here.
    
    
32. Z. Al-Ars and A.J. van de Goor, ``Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces,'' in Proc. Asian Test Symp. (12th ATS'03), Xian, China, November 17-19, 2003, pp. 24-27.
    Get paper here.
    
    
33. Z. Al-Ars and A.J. van de Goor, ``Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (11th IEEE MTDT'03), San Jose, California, July 28-29, 2003, pp. 27-32.
    Get paper here.
    
    
34. Z. Al-Ars, S. Hamdioui and A.J. van de Goor, ``A Fault Primitive Based Analysis of Linked Faults,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (11th IEEE MTDT'03), San Jose, California, July 28-29, 2003, pp. 33-39.
    Get paper here.
    
    
35. Z. Al-Ars, A.J. van de Goor, J. Braun and D. Richter, ``Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation,'' in Proc. Design, Automation and Test in Europe (6th DATE'03), Munich, Germany, March 3-7, 2003, pp. 484-489.
    Get paper here.
    
    
36. Z. Al-Ars and A.J. van de Goor, ``DRAM Specific Approximation of the Faulty Behavior of Cell Defects,'' in Proc. Asian Test Symp. (11th ATS'02), Guam, USA, November 18-20, 2002, pp. 98-103.
    Get paper here.
    
    
37. S. Hamdioui, Z. Al-Ars and A.J. van de Goor, ``Testing Static and Dynamic Faults in Random Access Memories,'' in Proc. IEEE VLSI Test Symp. (20th IEEE VTS'02), Monterey, California, April 28-May 2, 2002, pp. 395-400.
    Get paper here.
    
    
38. Z. Al-Ars and A.J. van de Goor, ``Approximating Infinite Dynamic Behavior for DRAM Cell Defects,'' in Proc. IEEE VLSI Test Symp. (20th IEEE VTS'02), Monterey, California, April 28-May 2, 2002, pp. 401-406.
    Get paper here.
    
    
39. Z. Al-Ars and A.J. van de Goor, ``Modeling Techniques and Tests for Partial Faults in Memory Devices,'' in Proc. Design, Automation and Test in Europe (5th DATE'02), Paris, France, March 4-8, 2002, pp. 89-93.
    Get paper here.
    
    
40. Z. Al-Ars, A.J. van de Goor, J. Braun and D. Richter, ``A Memory Specific Notation for Fault Modeling,'' in Proc. Asian Test Symp. (10th ATS'01), Kyoto, Japan, November 19-21, 2001, pp. 43-48.
    Get paper here.
    
    
41. Z. Al-Ars, A.J. van de Goor, J. Braun and D. Richter, ``Simulation based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs,'' in Proc. IEEE International Test Conference (32nd IEEE ITC'01), Baltimore, Maryland, October 28-November 2, 2001, pp. 783-792.
    Get paper here.
    
    
42. Z. Al-Ars and A.J. van de Goor, ``Transient Faults in DRAMs: Concept, Analysis and Impact on Tests,'' in Proc. IEEE International Workshop on Memory Technology, Design and Testing (9th IEEE MTDT'01), San Jose, California, August 6-7, 2001, pp. 59-64.
    Get paper here.
    
    
43. Z. Al-Ars and A.J. van de Goor, ``Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs,'' in Proc. Design, Automation and Test in Europe (4th DATE'01), Munich, Germany, March 13-16, 2001, pp. 496-503.
    Get paper here.
    
    
44. Z. Al-Ars, A.J. van de Goor, J. Braun, B. Gauch, D. Richter and W. Spirkl, ``Development of a DRAM Simulation Model for Fault Analysis Purposes,'' in Proc. 13th Workshop on Testmethods and Reliability of Circuits and Systems, Miesbach, Germany, February 18-20, 2001.
    Get paper here.
    
    
45. Z. Al-Ars and A.J. van de Goor, ``Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs,'' in Proc. Asian Test Symp. (9th ATS'00), Taipei, Taiwan, December 4-6, 2000, pp. 282-289.
    Get paper here.
    
    
46. A.J. van de Goor and Z. Al-Ars, ``Functional Memory Faults: A Formal Notation and a Taxonomy,'' in Proc. IEEE VLSI Test Symp. (18th IEEE VTS'00), Montreal, Canada, April 30-May 4, 2000, pp. 281-289.
    Get paper here.