![[]](../bullet.gif) Abstract:
The dynamic random access memory (DRAM) is the most widely used type of memory in the market today, due to its important application as the main memory of the personal computer (PC). These memories are elaborately tested by their manufacturers to ensure a high quality product for the consumer. However, this testing process is responsible for a large portion of the cost of these memories, standing now at 40% and gradually rising with each new generation. Companies usually develop the required memory tests in an ad hoc manner, relying heavily on an expensive combination of experience and statistics to construct the best test approach.
In this thesis, we propose a new alternative approach to the development of industrial memory testing that is more systematic and less expensive than the currently prevalent test approaches. The new approach
is based on the introduction of a number of fault analysis algorithms that enable the application of electrical Spice simulations to develop effective memory tests in a short amount of time. The new approach
makes it possible to enhance memory tests in many different manufacturing stages, starting from the initial test application stage where silicon is manufactured, through the memory ramp-up stage where products are shipped to the customer, and ending with the test adaptation stage, based on memory failures in the field. The new test development approach has been implemented and evaluated at Infineon Technologies,
a leading DRAM manufacturer, to develop tests for their DRAM products.
This thesis describes the details of the proposed test development algorithms, along with the way they are practically implemented for DRAM devices. Two different aspects necessary for DRAM tests are identified: test patterns and test stresses, then methods to generate and optimize both of them are proposed. In addition, the thesis discusses the results of applying the proposed approach to a large number of DRAM
defects, modeled from known DRAM failures on the layout level. Finally, the thesis ends with an elaborate case study to generate and optimize tests for a specific DRAM problem for which the new test development approach has proven its effectiveness.
Table of contents
1. Introduction
2. DRAM behavior and architecture
3. DRAM design and implementation
4. Modeling faulty memory behavior
5. Fault analysis approximation methods
6. Effects of bit line coupling
7. Application of the approximation method
8. Space of DRAM tests
9. Case study: the strap problem
10. Conclusions and recommendations
A. List of symbols
B. List of abbreviations
Errata
A PDF errata for the thesis can be downloaded here.
Analysis data
A huge body of analysis results and simulation data has been generated in the course of writing
this thesis to support the content. Most of the row data has not been presented in the thesis.
Here, it is possible to download most of the data files in PostScript format. There are three
main categories of result files: those generated for the 1D analysis in Section 7.3, those for the
2D analysis in Section 7.4, and those for the case study in Section 9.3.
|
