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Analysis of the Space of Functional
Fault Models and Its
Application
to Embedded DRAMs
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- Type: Masters thesis
- Date: October 1999
- Author: Z. Al-Ars
- Supervisor: Prof. Dr. Ir. A.J. van de Goor
- Number of pages: 261
- Technical Report number: 1-68340-28(1999)07
- Order: please contact me by e-mail
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Key words
Embedded DRAMs, circuit simulation, fault primitives, functional faults, functional tests
Abstract
Dynamic random access memories (DRAMs), the flagship
products of the semiconductor industry, are among the devices worst affected by
the imperfections in the production process of integrated circuits (ICs). This
results in a costly, time consuming test procedure, the price of which is
eventually payed by the end consumer. This report discusses the results of a
study made to analyze the faulty behavior of the embedded DRAM devices produced
by Siemens, Munich, Germany. The analysis is performed by injecting defects
into an electrical model of the memory, then simulating it for possible faulty
behavior. The results of the analysis can help produce more efficient test
procedures for the studied memory.
Table of contents
1. Introduction
2. Dynamic RAM arcitecture
3. Embedded DRAM structure
4. Functional fault models
5. Preparation for eDRAM simulation
6. Simulation of memory cell array opens
7. Simulation of memory cell array shorts
8. Simulation of memory cell array bridges
9. Conclusions and recommendations
Appendix A. Analysis of the MOS transistor behavior
Appendix B. Pstar input files
Appendix C. Fault analysis program
Errata
A PostScript errata for the thesis can be downloaded here.
Analysis data
Row data files in text format for the fault analysis can be downloaded here. Each file name gives the name of the analyzed
defect and the temperature of the analysis. For example, oc12.dat means that the file shows the fault analysis results
for defect OC1 and at a temperature of 27 C. The file content itself is coded. The description of the code is outlined
in the PostScript file here.
Below results for opens are given first, followed by shorts and bridges. All opens are analyzed at three temperatures: 27 C, 87 C, and 147 C. Shorts and bridges are analyzed at 27 C only.
OPENS
There are three types of opens: opens within cells (OC), opens on bit lines (OB), and opens in sense amplifiers (OS).
There are 4 opens within cells (OC):
There 10 opens on bit lines (OB):
There 8 opens in the sense amplifiers (OS):
SHORTS
There are 10 shorts analyzed at 27 C, 5 of them are shorts to Vdd while the other 5 are shorts to GND. The results for these 10 shorts are given in the following table.
BRIDGES
There are 13 analyzed bridges, 5 of which are within cells (BWC) while the other 8 are between cells (BBC). The faulty behavior of many of these bridges is the same. Therefore, only one result file is given for defects with equivalent faulty behavior.
| Bridges within cells |
BWC1-2 |
BWC3-4 |
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bwc1 |
bwc3 |
| Bridges between cells |
BBC1-2 |
BBC3-6 |
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bbc1 |
bbc3 |
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