Zaid's Books

Published books and theses

This page contains a description of the books and theses I wrote so far. Please, contact me if you are interested in getting any of them.

Title: Analysis of the Space of Functional Fault Models and Its Application to Embedded DRAMs

Type: Masters thesis
Date: October 1999
Author: Z. Al-Ars
Supervisor: Prof.dr.ir. A.J. van de Goor
Number of pages: 261
Technical report number: 1-68340-28(1999)07
Order: request your copy per e-mail

Abstract: Dynamic random access memories (DRAMs), the flagship products of the semiconductor industry, are among the devices worst affected by the imperfections in the production process of integrated circuits (ICs). This results in a costly, time consuming test procedure, the price of which is eventually payed by the end consumer. This report discusses the results of a study made to analyze the faulty behavior of the embedded DRAM devices produced by Siemens, Munich, Germany. The analysis is performed by injecting defects into an electrical model of the memory, then simulating it for possible faulty behavior. The results of the analysis can help produce more efficient test procedures for the studied memory.

Title: DRAM Fault Analysis and Test Generation

Type: PhD thesis
Date: June 2005
Author: Z. Al-Ars
Supervisor: Prof.dr.ir. A.J. van de Goor
Number of pages: 257
ISBN: 90-9019612-9
Order: buy your copy here

Abstract: In this thesis, we propose a new alternative approach to the development of industrial memory testing that is more systematic and less expensive than the currently prevalent test approaches. The new approach is based on the introduction of a number of fault analysis algorithms that enable the application of electrical Spice simulations to develop effective memory tests in a short amount of time. The new approach makes it possible to enhance memory tests in many different manufacturing stages, starting from the initial test application stage where silicon is manufactured, through the memory ramp-up stage where products are shipped to the customer, and ending with the test adaptation stage, based on memory failures in the field. The new test development approach has been implemented and evaluated at Infineon Technologies, a leading DRAM manufacturer, to develop tests for their DRAM products.