The main goal of the Delft WorkBench is to provide a semi-automatic tool platform for reconfigurable computing supporting the fully integrated and entire design process rather than isolated parts. It involves the following innovations of Methods, Algorithms and Techniques:

• Study of novel analysis algorithms based on reverse software engineering (automated or not) techniques;
• Study of a method for the automatic modification of the target compiler that takes into account the new system properties, including reconfigurable hardware extensions;
• Research of micro-coded techniques for the execution of benchmarked programs. The micro-code concepts are augmented to include hardware implementations in addition to instruction and function execution emulation;
• A method for mapping a working functionally equivalent design onto resources that are limited for its straight-forward implementation. Dynamic functionally equivalent transformations of a design will be investigated and implemented here.

Investigation of static and dynamic scheduling techniques for the MOLEN approach which separates reconfiguration and execution into two separate phases. This constitutes one of the most challenging parts of our research.

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Msc Research Topics

Code Profiling

Existing applications need to be analysed in order to identify interesting candidates for mapping on the FPGA. This analysis should be done using a set of criteria. These criteria should look at issues such as I/O, branches, arithmetic operations, etc. and result in a decision model that can be applied on any application. The outcome of this decision model should be a list of candidate functions that can be mapped on an FPGA.

The goal of the research is to propose such a decision model and to validate it focusing on a limited number of applications and doing preliminary calculations for performance improvement.

Library of FPGA configurations

A important aspect in designing a new architecture, the designer is confronted with a large variety of design choices. The goal of this research is to make a first step toward supporting this design space exploration process by establishing a library of (existing) FPGA mappings which can then be used for real evaluation on the Xilinx Virtex Pro. The data from these evaluations can then be used to construct a model that allows the designer to evaluate different designs prior to real implementation.

Automatic Compiler Support For Instruction Set Extension

Context:
Reconfigurable components such as Field Programmable Gate Arrays (FPGA's) are becoming increasingly popular and pose specific architectural challenges. One of those challenges is to automate the machine code generation process so that the proposed architecture extended with FPGA's can be tested and its performance evaluated by executing benchmark programs. To this purpose, the compiler needs to be retargeted in order to match the new architecture. There exist tools that automate a part of this retargeting process, namely the instruction selection phase. The goal of this Msc Topic is integrate the tool OLIVE into a compiler.

Problem statement:
Integration of the OLIVE code generator generator into the compiler included in Delft WorkBench Project and writing a specification for PowerPC Instruction Set with some extensions.