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1. B.H.H. Juurlink, I. Antochi, D. Crisu, S. D. Cotofana, S. Vassiliadis, GRAAL: A Framework for Low-Power 3D Graphics Accelerators, IEEE Computer Graphics and Applications, pp. 63-73, July 2008 (BibTeX)

2. I. Antochi, Suitability of Tile-Based Rendering for Low-Power 3D Graphics Accelerators, pp. 148, October 2007, PhD Thesis (BibTeX)

3. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Scene Management Models and Overlap Tests for Tile-Based Rendering, Proceedings of the EUROMICRO Symposium on Digital System Design, 2004 (DSD 2004)., pp. 424 - 431, Rennes, FRANCE, August 2004 (BibTeX)


4. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Memory Bandwidth Requirements of Tile-Based Rendering, Proceedings of the Third and Fourth International Workshops SAMOS 2003 and SAMOS 2004 (LNCS 3133), pp. 323-332, Samos, Greece, July 2004 (BibTeX)


5. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, GraalBench: A 3D Graphics Benchmark Suite for Mobile Phones, Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools, pp. 1-9, Washington, DC, USA, June 2004 (BibTeX)


6. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient State Management for Tile-Based 3D Graphics Architectures, Proceedings of the 15th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2004, pp. 336-340, Veldhoven, The Netherlands, November 2004 (BibTeX)


7. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient Tile-Aware Bounding-Box Overlap Test for Tile Based Rendering, Proceedings 2004 International Symposium on System-on-Chip, pp. 165-168, Tampere, Finland, November 2004 (BibTeX)

8. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, 3D Graphics Benchmarks for Low-Power Architectures, Proceedings of the 14th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2003, pp. 18-22, Veldhoven, The Netherlands, November 2003 (BibTeX)

9. I. Antochi, B.H.H. Juurlink, A. G. M. Cilio, P. Liuha, Trading efficiency for energy in a texture cache architecture, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems, pp. 189-196, Ischia, Italy, April 2002 (BibTeX)


10. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, Selecting the optimal tile size for low-power tile-based rendering, Proceedings ProRISC 2002, pp. 1-6, Veldhoven, The Netherlands, November 2002, Dutch Technology Foundation STW, Utrecht (BibTeX)


11. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, A Flexible Simulator for Exploring Hardware Rasterizers, 13th Annual Workshop on Circuits, Systems, and Signal Processing (ProRISC2002), Veldhoven, The Netherlands, November 2002 (BibTeX)


12. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, A low power 2D/3D graphics accelerator; A preliminary ISA, Delft Univerisity of Technology, pp. 40, Delft, The Netherlands, January 2002 (BibTeX)

13. I. Antochi, B.H.H. Juurlink, A. G. M. Cilio, A low-cost, power-efficient texture cache architecture, ProRISC 2001, pp. 250-257, Veldhoven, November 2001, ISBN: 90-73461-29-4 (BibTeX)