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Journal Articles

2010
  1. M Duranton, S. Yehia, B De Sutter, K De Bosschere, A Cohen, B Falsafi, G. N. Gaydadjiev, M. Katevenis, O. Temam, M. Valero, The HiPEAC Vision, High Performance and Embedded Architecture and Compilation, pp. 1-56, ICT-217068, Europe, January 2010 (BibTeX)

2008
  1. F. Martorell, S. D. Cotofana, A. Rubio, An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates, IEEE Transactions on Nanotechnology, pp. 24-33, January 2008, Vol. 7, No. 1 (BibTeX)

2007
  1. C.H. Meenderinck, S. D. Cotofana, Computing Division Using Single-Electron Tunneling Technology, IEEE Transactions on Nanotechnology, pp. 451-459, July 2007, Vol. 6, No. 4 (BibTeX)

  2. C.H. Meenderinck, S. D. Cotofana, An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology, Romanian Journal of Information Science and Technology, pp. 67-83, March 2007, Volume 10, number 1 (BibTeX)

2005
  1. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, Addition Related Arithmetic Operations via Controlled Transport of Charge, IEEE Transactions on Computers, pp. 243-256, March 2005, Vol. 54, No. 3 (BibTeX)

2004
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Single Electron Encoded Latches and Flip-Flops, IEEE Transactions on Nanotechnology, pp. 237-248, June 2004, Vol. 3, No. 2, (BibTeX)

  2. C. Hu, S. D. Cotofana, J. Jianfei, Q. Cai, Analog-to-Digital Converter Based on Single-Electron Tunneling Transistors, IEEE Transactions on VLSI Systems, pp. 1209-1213, November 2004, Vol. 12, No. 11 (BibTeX)

  3. C. Hu, S. D. Cotofana, J. Jianfei, Single-Electron Tunneling Transistor Implementation of Periodic Symmetric Functions, IEEE Transactions on Circuits and Systems II, pp. 593 - 597, November 2004, Vol. 51, No.11, (BibTeX)

  4. C. Hu, S. D. Cotofana, J. Jianfei, Digital to analogue converter based on single-electron tunnelling transistor, IEE Proceedings: Circuits, Devices and Systems, pp. 438- 442, October 2004, Vol. 151, No. 5 (BibTeX)




Conference Papers

2011
  1. M. Taouil, S. Hamdioui, Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 335-341, Cottbus, Germany, April 2011 (BibTeX)

  2. M. Taouil, S. Hamdioui, E.J. Marinissen, How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?, 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS11), Athens Greece, April 2011 (BibTeX)

2010
  1. , Seoul, Korea, August 2010 (BibTeX)

  2. A.J. van de Goor, S. Hamdioui, G. N. Gaydadjiev, Using a CISC microcontroller to test embedded memories , IEEE 13th international Symposium on Design and Diagnostic of Electronics Circuits and Systems (DDECS), pp. 261 - 266 , May 2010 (BibTeX)

  3. A.J. van de Goor, C. Jung, S. Hamdioui, G. N. Gaydadjiev, Low-cost, Customized and Flexible SRAM MBIST Engine, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 382 - 387 , Vienna, Austria, April 2010 (BibTeX)

  4. M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking, IEEE 19th Asian Test Symposium (ATS2010), Shanghai, China, December 2010 (BibTeX)

  5. On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs, IEEE International Test Conference (ITC 2010), Austin, Texas, USA, November 2010 (BibTeX)

  6. M. Taouil, S. Hamdioui, J. Verbree , E. J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs, IEEE International Test Conference (ITC 2010), Austin, Texas, USA, November 2010 (BibTeX)

  7. M. Taouil, S. Hamdioui, E.J. Marinissen, Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking, First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, pp. 6, Austin, Texas, USA, November 2010 (BibTeX)

2009
  1. A. Gbolagade, S. D. Cotofana, Residue-to-Decimal Converters for Moduli Sets with Common Factors, Proceedings of 52nd IEEE International Midwest Symposium on Circuits and Systems, ( MWSCAS 2009), pp. 624-627, Cancun, Mexico, August 2009 (BibTeX)

  2. B. Kuiper, S. D. Cotofana, Adaptive Clock Scheduling for Pipelined Structures, 2009 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 65-68, San Francisco, CA, USA, July 2009 (BibTeX)

  3. I.O. Agbo, S. Safiruddin, S. D. Cotofana, Implementable Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology, 9th IEEE Conference on Nanotechnology IEEE NANO 2009, pp. 450-453, Genoa, Italy, July 2009 (BibTeX)

  4. A.J. van de Goor, S. Hamdioui, G. N. Gaydadjiev, Z. Al-Ars, New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults, 18th IEEE Asian Test Symposium, pp. 391-397, Taichung, Taiwan, November 2009 (BibTeX)

  5. Z. Al-Ars, S. Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories, 18th IEEE Asian Test Symposium, pp. 403-408, Taichung, Taiwan, November 2009 (BibTeX)

2008
  1. S. Safiruddin, S. D. Cotofana, F. Peper, J. Lee, Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology, Procedeengs of the 8th IEEE Conference on Nanothechnology, Arlington, Texas, USA, August 2008 (BibTeX)

  2. S. Safiruddin, S. D. Cotofana, F. Peper, Single Electron Tunneling Delay Insensitive and Fluctuation Based Computation Paradigms and Circuits, Proceedings of the 2008 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 69-76, Anaheim, California, USA, June 2008 (BibTeX)

2007
  1. S. Safiruddin, S. D. Cotofana, Building Blocks for Delay-Insensitive Circuits using Single Electron Tunneling Devices, Proceedings of the 7th IEEE International Conference on Nanotechnology, pp. 704-708, Hong Kong, August 2007 (BibTeX)

  2. F. Martorell, S. D. Cotofana, A. Rubio, Fault Tolerant Structures for Nanoscale Gates, Proceedings of the 7th IEEE International Conference on Nanotechnology, pp. 605-610, Hong Kong, August 2007 (BibTeX)

  3. S. D. Cotofana, On Effective Computation with Single Electron Devices, Proceedings of the 22nd Conference on Design of Circuits and Integrated Systems (DICS2007), pp. 293-298, Sevilla, Spain, November 2007 (BibTeX)

  4. F. Martorell, S. D. Cotofana, A. Rubio, Manufacturability Issues of Redundant Nanogates, Proceedings of 2007 IEEE International Semiconductor Conference, pp. 49-52, Sinaia, Romania, October 2007 (BibTeX)

2006
  1. C.H. Meenderinck, S. D. Cotofana, Basic Building Blocks for Effective Single Electron Tunneling Technology Based Computation, Proceedings of International Semiconductor Conference (CAS2006), pp. 57-62, Sinaia, Romania, September 2006 (BibTeX)

  2. D. Milosavljevic, S. D. Cotofana, A Method to Analyze the Fault Tolerance of Molecular Quantum-Dot Cellular Automata Systems, Proceedings of International Semiconductor Conference (CAS2006), pp. 399-402, Sinaia, Romania, September 2006 (BibTeX)

  3. C.H. Meenderinck, S. D. Cotofana, Computing Division in the Electron Counting Paradigm using Single Electron Tunneling Technology, proceedings of the 6th IEEE Conference on Nanotechnology, Cincinnati, Ohio USA, July 2006 (BibTeX)

  4. C.H. Meenderinck, S. D. Cotofana, High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology, Proceedings of the 6th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2006), pp. 447-456, Samos, Greece, July 2006 (BibTeX)

  5. C.H. Meenderinck, S. D. Cotofana, Electron Counting based High-Radix Multiplication in Single Electron Tunneling Technology, Proceedings of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 4571-4574, Kos, Greece, May 2006 (BibTeX)

2005
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Buffer Design Trade-Offs for Single Electron Logic Gates, Proceedings of 2005 5th IEEE Conference on Nanotechnology, pp. (CD proceedings), Nagoya, Japan, July 2005, Best paper award (BibTeX)

  2. C.H. Meenderinck, C. R. Lageweg, S. D. Cotofana, Design Methodology for Single Electron Based Building Blocks, Proceedings of 2005 5th IEEE Conference on Nanotechnology, pp. (CD proceedings), Nagoya, Japan, July 2005 (BibTeX)

  3. C.H. Meenderinck, S. D. Cotofana, C. R. Lageweg, High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology, Proceedings of 16th International Conference on Application-Specific Systems, Architectures and Processors, pp. 294-299, Samos, Greece, July 2005 (BibTeX)

  4. C.H. Meenderinck, S. D. Cotofana, Computing Periodic Symmetric Functions in Single Electron Tunneling Technology, Proceedings of International Semiconductor Conference (CAS), pp. 47-50, Sinaia, Romania, October 2005, Best paper award (BibTeX)

2004
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Binary Multiplication Based on Single Electron Tunneling, proceedings of the 15th International Conference on Application-specific Systems, Architectures and Processors, pp. 152-166, Galveston, USA, September 2004 (BibTeX)

  2. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Binary Addition based on Single Electron Tunneling Devices, Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD proceedings), Munich, Germany, August 2004 (BibTeX)

  3. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Effective Computation with Nanodevices: A single Electron Tunneling Case Study, Proceedings of the 2004 International Semiconductor Conference (CAS 2004), pp. 41-50, Sinaia, Romania, October 2004, Invited Paper (BibTeX)

2003
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Single Electron Encoded Logic Memory Elements, proceedings of 3rd IEEE International Conference on Nanotechnology, pp. 449-452, San Francisco, USA, September 2003 (BibTeX)

  2. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge, proceedings of 16th IEEE Symposium on Computer Arithmetic, pp. 245-252, Santiago de Compostela, Spain, June 2003 (BibTeX)

  3. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Evaluation Methodology for Single Electron Encoded Threshold Logic Gates, proceedings of the IFIP International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC), pp. 258-262, Darmstadt, Germany, December 2003 (BibTeX)

2002
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A full adder implementation using SET based linear threshold gates, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002, pp. 665-669, Dubrovnik, Croatia, September 2002 (BibTeX)

  2. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Static buffered SET based logic gates, Proceedings of the 2002 2nd IEEE Conference on Nanotechnology, pp. 491-494, August 2002 (BibTeX)

2001
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A linear threshold gate implementation in single electron technology, Proceedings. IEEE Computer Society Workshop on VLSI 2001: Emerging Technologies for VLSI Systems, pp. 93-98, Orlando, USA, April 2001 (BibTeX)

  2. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Achieving fanout capabilities in single electron encoded logic networks, Proceedings. Vol. 2. 6th International Conference on Solid-State and Integrated Circuit Technology, pp. 1383-1386, Shanghai, China, October 2001 (BibTeX)

  3. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Digital to analog conversion performed in single electron technology, proceedings. 1st IEEE Conference on Nanotechnology, pp. 105-110, Maui, USA, October 2001 (BibTeX)

1987
  1. , November 1987 (BibTeX)




PhD Theses

2004
  1. C. R. Lageweg, Single Electron Tunneling Based Arithmetic Computation, The Hague, The Netherlands, November 2004, ISBN 90-9018686-7, PhD Thesis (BibTeX)




MSc Theses

2008
  1. S. Safiruddin, Single Electron Tunneling Based Building Blocks for Delay Insensitive Circuits, June 2008, CE-MS-2008-02, MSc Thesis (BibTeX)

2005
  1. C.H. Meenderinck, Arithmetic Operations in Single Electron Tunneling Technology, July 2005, MSc Thesis (BibTeX)

  2. D. Milosavljevic, Fault Tolerance of Molecular Quantum-Dot Computing Automata Systems, CE-MS-2005-10, December 2005, MSc Thesis (BibTeX)