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The NanoC MSc Projects
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Late comers: An analysis of flip-flop behavior and performance under late arriving input data
Context:
One of the issues the NanoC project addresses is performance degradation due to delay variations in Deep Sub-Micron (DSM) technology.
The size of transistors and wires has been decreasing since decades and has entered the area of deca-nanometers (100 nm).
Small imperfections, like deviations in the transistor channel length, are now becoming significant and cause the delay of a
gate to have a certain variance. Also environmental variations, like temperature, cause delay variations.
If no appropriate action is taken, delay variation might lead to timing violation, that is a data signal might arrive to late at the
input of a flip-flop. One way to alleviate this problem is to increase the clock period (reduce operation frequency) but this is not
advantageous as it may result in significant performance degradation. In the NanoC project, we seek a mechanism that is able to monitor
delay variations and undertake appropriate counteractions with no or few performance loss.
Problem statement:
In order to be able to find a solution, it is necessary to have a good understanding of the problem that we are dealing with. One of the
issues which has not been researched yet is the behavior of flip-flops for late arriving data signals. If a data signal is in time, it
is clocked and the input value appears at the output some time after the clock edge. If a data signal arrives too late, it is not
clocked as it should and the output of the flip-flop will not change according to the input.
The question is, what happens in between? Related to this question there are many aspects we would like to investigate. What happens
to the clock-to-output delay of the flip-flop? What happens to the power consumption? It is known that a flip-flop can end up in a metastable
state (the output is halfway logic '1' and logic '0'). Will such a situation be induced by late arriving input data?
Expected effort:
The student is expected to investigate the behavior of several types of flip-flops for late arriving data signals. For that purpose a
number of state of the art flip-flop implementations have to be selected. The selected flip-flops will be simulated at circuit level
(SPICE) in various operating conditions and the delay and the power consumption will be measured. Based on these experiments, the student
may eventually propose ways to improve the flip-flops performance for late arriving input data.
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SIMON front end; an user interface for a nano electronics simulator
Context:
In the NanoC project we have been investigating Single Electron Tunneling (SET) technology for a while and have proposed several ways
to implement arithmetic operations using SET technology. To verify our arithmetic circuits we are using a simulator called SIMON, which is
one of the two available simulators for SET technology.
Problem statement:
The user interface of SIMON is very basic and definitely not ergonomic. Building large circuits constitutes a major problem as there is no
copy-paste function, and neither does the software component libraries. Another issue is setting the input signals, which are hard to
program and are stored in the circuit description. To simulate a circuit for different input sets, different circuits have to be stored.
Now, changing a circuit parameter means that all stored circuit descriptions have to be adjusted. Further we deal with a limited
drawing area, which sometimes is too small. We also would like to be able to re-use output signals as input signals. At the moment
the simulator can only measure voltage, current and charge. If possible we would also like the circuit to measure energy consumption and delay.
Expected effort:
The student is expected to make an in-depth investigation of the problems with the current user interface used in SIMON. Beside the
problems we experience, the student is expected to come up with other improvements, for which an investigation of other simulators
might be necessary. The student will define and present a detailed plan for a front interface which, if accepted, will be implemented.
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Connecting SIMVA simulator with SystemC
Context:
One of the issues the NanoC project addresses is performance degradation due to delay variations in Deep Sub-Micron (DSM) technology. The size of transistors and wires has been decreasing since decades and has entered the area of deca-nanometers (< 100 nm). Small imperfections, like deviations in the transistor channel length, are now becoming significant and cause the delay of a gate to have a certain significant variance. Also environmental variations, like temperature, cause delay variations.
If no appropriate action is taken, delay variation might lead to timing violation that is a data signal might be wrongly sampled due to the fact that it arrived too late at the input of a flip-flop. Such a situation may have catastrophic consequences as it may damage the overall processor calculation. One way to alleviate this problem is to increase the clock period (reduce operation frequency) but this is not advantageous as it may result in significant performance degradation. In the NanoC project, we seek a mechanism that is able to monitor delay variations inside circuits and undertake appropriate counteractions with no or few performance loss.
Problem statement:
In order to be able to find a solution, it is necessary to have a good understanding of the problem that we are dealing with. Therefore we have created a simulator for variations in a pipelined structure, called SIMVA. So far the general framework of the simulator has been build. We are able to induce delay variations that have various statistic profiles but for the time being the pipeline stages are dummy structures that can only generate random data outputs. While our preliminary experiments clearly indicate that there are plenty of opportunities we can use in our quest for a design for variability framework, in order to make further steps towards a solution we need to be able to simulate the behavior of real circuits under delay variation conditions. The creation of such an environment in which the dummy pipeline stages can be replaced with real life designs (processor pipeline stages) constitutes the goal of the present master thesis project.
Expected effort:
The student is expected to define and implement an interface that can connect our SIMVA simulator with a SystemC simulation environment. The student will have to study the available SystemC simulators and select the one that seems the most appropriate for joint work with SIMVA. Next, the student has to build the interface between SIMVA and the SystemC simulator. For a given design and certain delay variation conditions the simulator has to be able to provide the values and the associated delay for all the relevant signals in the under consideration pipeline stages. This means that apart of the circuit structure somewhere along the line variations have to be included in the circuit model. The student is expected to investigate how this can be done in the best way. After the interface is defined and implemented, the student has to investigate available benchmarks, select a set of SIMVA simulator relevant ones, and carry on some simulation experiments for debug and test purpose.
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Fault Tolerance Simulation for Quantum-Dot Cellular Automata
Context:
Quantum-Dot Cellular Automata (QCA) is a novel nano technology where binary values are represented by charge distribution within the QCA cells. Computation elements as AND, NOT, and OR gates can be constructed by placing groups of QCA cells together in particular geometrical configurations and their correct functionality strongly depends on the geometrical positions of the cells. Given that positional errors are unavoidable, we study the fault tolerance of QCA computational structures to errors induced by the fabrication process.
Problem statement:
Simulating the effects of QCA cell displacement consists of a few steps, each utilizing its own software. So far, the output of one simulation step is manually translated to the input of the next step, which requires a lot of work and is very error prone. We would like to have some software tool that can automatically take the output of one step and generate out of it, the input for the next step.
Expected effort:
The student is expected to study QCA technology and get acquainted with the simulation software we use. Next the student is expected to write software programs that can translate the output of one simulator to the input of the next. Further, the student has to investigate possibilities for creating a QCA simulation environment, which allows for a user friendly control of all simulators and software involved. Possibly this environment can also contain some tools that aids the user to quickly build the computational structures he/she wants to simulate.
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