The NANO Project Description

Single electron based computation

During the last decades we have witnessed spectacular increases in the performance of semiconductor based computation. Since the seventies the microelectronics industry has followed Moore's law, doubling processing power every 18 months. This has been driven by a combination of advances in device technology and computer engineering. The ever decreasing feature size of the transistor, and the corresponding increase in the number of transistor per square centimeter, has created the basis for major advances.

At the same time there are limits to the reduction of the physical dimensions of the transistor as we currently know it (estimated to be somewhere in the order of 10 nm). The International Technology Roadmap for Semiconductors predicts that this level will be reached in the next decade. Therefore, to maintain the current exponential growth in packing density, technologies based on alternative principles are increasingly being investigated. One promising candidate is Single Electron Tunneling (SET). Key merits of the SET technology are its potential for sub-nanometer feature size scaling, room temperature operations, and ultra-low power consumption.

SET circuits are centered around the tunnel junction, through which individual electrons can be transported in a controlled manner. However, looking at the research carried out on SET based logic circuits, we notice that most studies are focussed on the SET transistor (whose behavior mimics that of the MOS transistor). Although this has the advantage that existing CMOS transistor-based designs can easily be ported to SET technology, it does not fully utilize the potential of the SET technology. The main disadvantage of the CMOS like design style is that the current transport though an 'open' transistor still consists of a large number of individual electrons 'dripping' through the tunnel junctions. This is obviously a far slower process then the transport of just one single electron through the same junction.

Our research focuses on the implementation of logic functions in SET technology, using the SET tunnel junction's unique behavior. We currently pursue the following two main lines of research:

• Single Electron Encoded Logic: In traditional logic, the Boolean value 0 and 1 are usually encoded as an amount of charge that is stored on a gate's output node(s). Even with state-of-the-art CMOS, switching the output value of a gates results in the transport of hundreds of electrons. Given that with the SET technology we can control the transport of individual electrons, we have the potential to create logic gates in which the Boolean logic values 0 and 1 are encoded as a net charge of 0 and 1 electron charges only. By limiting charge transport to just 1 electron, we ensure a minimum power consumption while maximizing the switching speed of the gates.
• Electron Counting Arithmetic: Current computational circuits are (almost exclusively) based on Boolean logic calculus. However, the ability to control the transport of individual electrons in SET technology introduces a broad range of new possibilities and challenges for implementing computer arithmetic circuits. Instead of representing numbers by binary values, we can encode them as an amount of electrons the is present in a charge reservoir. This opens up the possibility to perform arithmetic operations via the controlled transport of charge. An addition for example could consists of adding the contents of two charge reservoirs.

The research angles described above are only two possible approaches. For an overview of the results of this research, please have a look at our publications.