It is strongly advised that the student has finished most
course work before applying for a MSc project in the industry.
Furthermore, international MSc students may require a 'work permit'
before they can start their work. Obtaining such a permit may take
approximately 2 months. It is advisable to start looking early for
an open position and to start your preparatory work while waiting for
the permit to be issued. More information can be found on
this page. Please contact Jan de Vries (j.devries@@tudelft.nl)
if you're interested to get credit points based on work performed in the industry.
If you're interested in performing an internship in the industry and
would like to get credit points based on your work, lease contact
Jan de Vries (j.devries@@tudelft.nl). More information about this
procedure can be found on
this page.
It is also possible for students to find industrial MSc projects by
themselves. In this case, the project must be approved first. You
should contact Zaid Al-Ars for more details on how to obtain approval.
2012
- CODE: CE2012-4
Title: Modeling and Simulation of Large-Scale Networks
Project Description:
Designing large-scale sensor networks is an extremely demanding task, as it amounts on a complex balance among many (frequently contradicting) requirements and constraints. The design process should be supported by a proper set of tools, which - using various models such as functional, power consumption and failure - can simulate the operation of the network and quantitatively can characterize the performance of the different design alternatives. Hence, assist the designer to make the proper design choices. The programs running on the (wireless) nodes are components of the design. Their behavior has significant impact, even beyond the functional perspective of the system. Due to the large-scale character of the system it is not feasible to execute the programs instruction by instruction. Rather models of the programs should be used, which reflect all relevant feature of the program but do not need instruction level execution.
Problem statement:
The assignment investigates the different approaches for modeling program execution. A modeling proposal should be developed, which satisfies the needs of the quantitative evaluation of sensor network architectures. Simulator should be developed, which executes the application program models and measures the execution performance.
Company Name: TNO
Company Description: TNO is an independent research organisation whose expertise and research make an important contribution to the competitiveness of companies and organisations, to the economy and to the quality of society as a whole. TNO’s unique position is attributable to its versatility and capacity to integrate this knowledge.
Qualifications: (none)
Location: The Hague, The Netherlands
Start date: June 2012
Duration: 9 months
Number of positions: MSc project
Comment(s): (none)
- CODE: CE2012-3
Title: System-wide Optimization of Distributed Dynamic Sub-systems
Project Description:
Optimization techniques for dynamic systems is a well developed area of expertise with great practical significance (e.g., joint optimization of traffic lights, power network maintenance, control of renewable energy sources, etc.). In systems that are spatially distributed (i.e., a network of multiple subsystems), the observations from the process cannot be communicated centrally and thus optimization can only be done locally by each subsystems. The question is how the local optimizers should interact in order to achieve global optimum. The problem is especially interesting in wireless sensor networks, where the number of subsystems is high and the communication/power constraints are serious.
Problem statement:
The assignment should overview the different types of distributed optimization problems and develop solutions for particular large-scale mobility related optimization cases (typical cases: traffic light management, cooperative highway on-ramp control).
Company Name: TNO
Company Description: TNO is an independent research organisation whose expertise and research make an important contribution to the competitiveness of companies and organisations, to the economy and to the quality of society as a whole. TNO’s unique position is attributable to its versatility and capacity to integrate this knowledge.
Qualifications: (none)
Location: The Hague, The Netherlands
Start date: June 2012
Duration: 9 months
Number of positions: MSc project
Comment(s): (none)
- CODE: CE2012-2
Title: Adaptive Voltage Scaling and IC Production Testing
Project Description:
Many processor chips manufactured today apply voltage scaling to reduce power consumption and ensure reliable functionality under process variability. Traditional techniques to voltage scaling require running devices at worst-case voltage conditions, which leads to additional power consumption, and to increasing design margins. Adaptive voltage scaling technique makes it possible to use an optimal voltage setting per IC to compensate for process & temperature variations. The challenge is to be able to determine in an accurate manner the performance of the die at a specific voltage, and also to compensate for intra-die variations. Adaptive voltage scaling will also affect traditional IC production testing since design margins are minimized for each die in a real application, and hence leads to some adaptive testing by reducing test margins as well. Since manufacturing and application environments can be different, test margins must be carefully analyzed to avoid potential yield overkill.
Problem statement:
The first issue is to generate an equation to accurately predict the minimum estimated transistor voltage per IC, relying on a variety of ring oscillators with different properties (transistors, RC), and on structural testing (ATPG, MBIST). The second issue is to define specific design rules (ring oscillator layout placements, properties, design rules) to improve equation accuracy.
Expected effort:
A good working knowledge of statistics and regression will be appreciated. The candidate should be able to understand digital CAD flow from RTL to GDS. The following tasks need to be carried out.
Task 1: 28n-32n SoC test data analysis to check for best predictors
Task 2: Equation generation and yield estimation modeling
Task 3: AVS test flow requirements
Task 4: IC design variability analysis
Company Name: ST-Ericsson
Company Description: (none)
Qualifications: (none)
Location: Grenoble, France
Start date: April 1, 2012
Duration: 9 months
Number of positions: 1 MSc
Comment(s): (none)
- CODE: CE2012-1
Title: Optimization of Parallel Video Processing Programs on Multicore/GPU Platforms
Project Description:
Thomson Video Networks, within the video coding lab, develops libraries that are embedded into broadcast/WebTV/IPTV systems. These programs are usually computationally intensive and require optimization for the hardware platforms used. One of programs being used in the coding group, a video characterization module, performs a standard signal processing algorithm. Parts of this program have been identified that could be parallelized. This can be checked against existing automatic tool results (par4all). The activities required by the intern start by the annotation of this program using OpenCL pragmas, and then to measure the results on server and desktop platforms (with and without GPU). Performance analysis will be conducted within the video coding lab under with the help of the supervisor, to identify possible architectural optimizations. The internship will bring the intern into real professional product development, and let them develop experience in agile methods, programming and advanced Intel platforms architectures (servers, GPUs).
Company Name: Thomson Netwroks
Company Description: Thomson Video Networks is an international company in the professional broadcast and creation of video content. Their Rennes facility is a 350 people R&D center dedicated to video compression and broadcast equipment and systems, on various networks types, for telcos and broadcasters.
Qualifications: (none)
Location: Rennes, France
Start date: Beginning of 2012
Duration: 6 months
Number of positions: Internship
Comment(s): (none)
2010
- CODE: CE2010-10
Title: Pattern recognition in a wireless network of LED lamps (MSc or internship)
Project Description:
Philips Applied Technologies has a system setup of a dozen of lamps that all contain a PIR sensor and that are have wireless communication with each other. We would like to analyze the patterns that are emerging in the activations of these lamps in order to optimize the switching of the lamps and to extract information on their physical positioning. The current system is able to transmit the radio messages and the demonstrator contains some basic algorithms that analyze the activation patterns. We would like to extend these algorithms to recognize more complex patterns and to show more advanced behavior.
From this project we expect the following deliverables:
o A substantial improvement of our algorithms, covering more and more advanced patterns
o Implementation of the algorithms on the embedded network chips (TI 2530)
o An updated prototype containing the improved algorithms
Company Name: Philips Research
Company Description: (none)
Qualifications: We are looking for a student that has completed his bachelor and is now enlisted in a Master of Science program; the assignment could be part of a thesis work (in embedded systems, wireless sensor systems and/or machine learning/pattern recognition/applied mathematics) or be filled in as a summer internship. (Minimum 6 months)Study areas we are looking for: Computer Sciences, Electronics, Engineering, Mathematics and Software Technology.
To be successful in this internship you:
• Have experience in developing embedded software (especially the TI 2530 would be a plus)
o Have mathematical maturity in probability theory/statistics
o Have experience with machine learning or pattern recognition (would be a plus)
o Are fluent in oral en written English
Location: Eindhoven
Start date: as soon as possible
Duration: 3 to 9 months
Number of positions: 1
Comment(s): When you apply we expect to receive both Cover Letter (outlining your motivation and informing your availability) and Resume. Please also note that in order to be applicable for an Internship, it should be compulsory (outside EU/EER) by your education and you need to be registered as a student, formal documentation of which may be requested at any time.
- CODE: CE2010-09
Title: Analog Tuner Integration (MSc or internship)
Project Description:
Due to a System-in-Package (SiP) structure of the receiver solution, a number of issues arise when considering the integration of the analog tuner die in a single package together with digital subsystems:
o Selection of passives - for SiP integration it is in general advisable to limit the number of passive components used around the tuner die to minimum. On the other hand there are strict requirements regarding sensitivity, linearity and robustness against inter-channel interference which highly depend on a correct selection of these components. This results in a trade-off concerning the amount, value and type of passive components used together with the tuner inside the SiP which should be optimized before making final integration decisions.
o Automatic Gain Control (AGC) - the tuner under evaluation provides multiple mechanisms for gain control. Except for a coarse AGC implemented in the tuner itself which uses a wide-band power detector, gains on various down-conversion stages can be controlled based on narrow-band signal power estimation performed in the digital demodulator. The narrow-band power estimation algorithms, gain control decision policies and finally selection of an appropriate AGC interface should be jointly investigated in various reception environments.
o Tuner clocking scheme - there are multiple ways of providing frequency reference to the tuner in question including quartz crystal reference exclusive to the tuner die, sharing a quartz crystal between the tuner die and digital demodulator die and finally providing a CMOS clock waveform to the tuner die from a clock signal generator included in the digital die. All three scenarios should be evaluated regarding ease of implementation in a SiP environment and their impact on receiver sensitivity.All experiments should be targeting the wireless broadcast standards DAB, DAB+, T-DMB and FM-RDS.
Assignment
o Designing the experiments mentioned in problem description
o Assembling an integrated lab bench test environment based on available components
o Performing and documenting the experiments
o Presentation of conclusions
Company Name: Recore Systems
Company Description: Recore Systems is a reconfigurable computing company that provides IP (intellectual property) for creating advanced digital signal processing platform chips. The company was established in 2005 and is based in Enschede, The Netherlands.
Recore enables chip manufacturers to double design productivity and improve both energy consumption and performance. Recore's Montium TM technology comprises innovative processor cores, design tools for easy integration in customer solutions and ready-to-use applications. This technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems.
Recore is a service oriented company offering application IP libraries for Montium platforms, application engineering for Montium platforms, IDE tools for Montium platforms and hardware IPs.
The reconfigurable Montium TM technology is based on more than 7 years of research and development. The result is a (multi)processor architecture that satisfies the combination of extremely low power consumption, high performance, flexibility and low costs. Use of ready-to-use hardware IP reduces the escalating chip development costs and time by more than 50%.
Recore's design tools allow the application engineer to easily implement applications. This expedites the design cycle of new applications, whilst significantly reducing engineering overheads. Recore develops several design tools in synergy with its hardware cores, and offers a comprehensive set of Montium software design tools.
Recore has a strong focus on providing applications for its processor cores. Programmability and the (re)use of standard application IP blocks lead to a short design cycle for new applications.
Recore Systems offers students to experience a dynamic work environment that values a hands-on mentality and creativity. The culture within the company is informal and the communication lines are short. Recore is a rapidly growing company and there are ample opportunities to develop personal skills.
Qualifications: Electrical Engineering or Computer Engineering with background in analog design.
Location: Enschede
Start date: as soon as possible
Duration: 3 to 9 months
Number of positions: 1
Comment(s): Available resources
o Analog tuner evaluation kit
o Multiple Analog-Digital Converter boards
o FPGA development kit for emulating digital demodulator functionality
o Spectrum M2i.6011 dual-channel arbitrary waveform generator
o Custom modulation software for DAB, DAB+ and T-DMB standards
o HP/Agilent E4431B RF generator with vector modulation (IQ) support
o DAB / DAB+ / T-DMB reference demodulator software model (C++) including BER evaluator
- CODE: CE2010-08
Title: Star Tracker Development (internship)
Project Description:
ISIS is currently developing an advanced star-tracker to complete its range of attitude determination subsystems. The most innovative aspect of the star tracker is that it will perform within an envelope of about 50x100x100 millimeters. The sensor will be compatible with the CubeSat standard and the limited on-board resources available for nano-satellites. We are currently looking for an engineer to work on embedded implementation of the camera read-out and the interfacing electronics. The project aims to achieve the following objectives
- MSc / BSc Computer Engineering or similar education
- Affinity with space technology
- Fluent in English
- Knowledge of FPGAs and microcontrollers
- Knowledge of C, C++
- Knowledge of VHDL.
- Experience with digital electronics
- Knowledge of image processing (preferred)
Company Name: ISIS
Company Description: ISIS (Innovative Solutions In Space) is a young and dynamic company in the space industry. The company specializes in the miniaturization of satellite systems with a particular emphasis on the design and development of subsystems for micro- and nanosatellites. Located in the Netherlands in Delft, ISIS supports small satellite projects and missions with its services and products.
Qualifications: The student is expected to have the following profile
- MSc / BSc Computer Engineering or similar education
- Affinity with space technology
- Fluent in English
- Knowledge of FPGAs and micro-controllers
- Knowledge of C, C++
- Knowledge of VHDL.
- Experience with digital electronics
- Knowledge of image processing (preferred)
Location: Delft
Start date: as soon as possible
Duration: 5 months
Number of positions: 1
Comment(s): (none)
- CODE: CE2010-07
Title: Low-power Processor Design
Project Description:
Silicon Hive's processors employ many architectural features to decrease power consumption. Besides supporting all types of parallelism, they have loopcaches, singleinstruction loops, RTL clock gating, operand isolation, synchronous register files, etc. All these features are implemented at RTL level. However, in advanced process nodes, static power consumption increases. The current practice of course-grain power islands and power switching needs to be refined. On these finer grain power islands, both the clock and the voltage need to be made scalable with the clock speed requirements of the application. This way, since power is FxVxI, power islands can reduce power consumption by a power of 3. Traditionally power switching is introduced at system level. However, we expect much better results from applying power islands within Silicon Hive cores. Silicon Hive actively cooperates in a number of international projects with companies such as Cadence, ST Microelectronics, Philips, NXP, and IMEC to achieve these goals.
First of all, extensive experiments and characterization are needed to find optimal granularity. Secondly, when parts of circuits are switched off, they loose all state information. This data needs to be saved and restored when power is switched back on. Strategies for such state retention need to be developed. Power switching and voltage/clock scaling should be controlled by the compiler and thus require new compiler hooks. Lastly power islands need additional hardware at the boundaries to level voltage differences and isolate power-down circuits from active circuits.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering or Computer Engineering with an analytical mind and knowledge in computer architecutre and VLSI design.
Location: Eindhoven
Start date: as soon as possible
Duration: 9 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
- CODE: CE2010-06
Title: Ontwikkeling van een XSD vereenvoudiging- en compressiemechanisme (internship)
Project Description:
Met de groei van het aantal implementaties van Service Oriented Architecture (SOA) groeit de behoefte aan inrichting van test- en validatiefunctionaliteit voor web services. Oelan is gespecialiseerd in het testen en valideren van SOA.
Een toenemend probleem is de complexiteit van de interfacebeschrijvingen van web services (WSDL files). Web service operaties die gedefinieerd worden in WSDL files bevatten gegevensdefinities die zijn vastgelegd m.b.v. XML schema definities (XSD). Schema's refereren vaak aan andere schema's. Het resultaat is een sterk geneste boomstructuur, waarvan slechts een fractie benodigd is, maar die bij het verwerken (parsen) vaak leidt tot problemen en een grote systeembelasting.
De doelen van de stage zijn:
onderzoek te doen naar mogelijkheden tot inzichtelijk maken van XSD boomstructuren
onderzoek doen naar mogelijkheden tot vereenvoudiging van XSD boomstructuren.
een prototype te ontwikkelen van een applicatie die XSDs comprimeert en uitgenereert.
De opdracht is een combinatie van onderzoek en ontwikkeling. Van de stagiair wordt verwacht dat hij/zij affiniteit heeft met software development. Hierbij dient zoveel mogelijk gebruik worden gemaakt van 'open source' software en Java.
Company Name: Oelan
Company Description: Oelan begeleidt organisaties bij het bereiken van hun bedrijfs- en projectdoelstellingen. Oelan zorgt voor de aansluiting tussen de continue veranderende business en de hiervoor benodigde flexibele IT met een focus op service gerichte architectuur (SOA).
Qualifications: Deze stageopdracht is bedoeld voor iemand die de combinatie van research en development interessant vindt.
Om de opdracht te kunnen uitvoeren is kennis noodzakelijk van XML, XSD en XML Document Object Model en Java. Kennis van Unix/Linux is een pre.
Location: Amsterdam
Start date: zo snel mogelijk
Duration: 3 to 6 months
Number of positions: 1
Comment(s): Oelan biedt een stage- en reiskostenvergoeding aan.
- CODE: CE2010-05
Title: IP-XACT System-Level Description Formalism (internship)
Project Description:
Silicon Hive is one of the founding members of the EU-supported FP7 project, called MADNESS (Methods for predictAble Design of heterogeNeous Embedded System with adaptivity and reliability Support). In this project, universities from Italy, Switzerland, and Netherlands work together with industrial partners (Lantiq, ICD, Silicon Hive) to create a methodology for automating the design space exploration of complex multi-processor systems. IP-XACT is a standard language for the description of SoC systems.
The assignment in this project will consist of developing a tool to translate between the IP-XACT system description language and HSD (Hive System Description language). Such a tool is an essential component of the MADNESS project, as it allows the project partners to work with each other's system descriptions and to generate optimized multi-processor systems which can then be used by Silicon Hive's HSD tooling to generate actual implementations and compile actual applications onto the generated systems.
The candidate(s) will analyze the system description languages, as provided by IP-XACT and HSD to determine the requirements for the translator tool. Then, a design for both the HSD-to-IP-XACT and the IP-XACT-to-HSD the translator tools will be developed. The tools will be implemented using Silicon Hive's CT compiler compiler toolset. This toolset is similar, but more powerful, than the open source LEX and YACC tools.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering, Computer Engineering, or Computing Science, with an analytical mind and skilled in algorithm development and implementation in C/C++.
Location: Eindhoven
Start date: as soon as possible
Duration: 3 to 6 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
- CODE: CE2010-04
Title: Free Viewpoint 3D TV (internship)
Project Description:
Silicon Hive's HiveFlex VSP family of processors is specifically targeted at video signal processing. It is applied in video codecs for such standards as H.264, MPEG-4, and Microsoft VC. Currently, some of these standards are being extended to support 3D video. This means that, next to regular 2D video, streams will encode additional depth information.
Silicon Hive is cooperating in the European project iGLANCE (http://iglance.org/), in which it intends to extend its VSP processors with specific features to decode this depth information. After this decoding, the multiple images have to rendered for the different viewing angles of different users. This means that the video and depth data have to be rendered as multiple stereo images, depending on the viewing angle of the user. Eventually, the system will have to respond to viewers choosing arbitrary viewing angles around the scene. In both cases, occlusion information has to be calculated for objects that were partially or completely hidden behind other objects in the original 2D streams.
The candidate(s) will analyze the architecture of the existing VSP processor and emerging 3D extensions to video coding standards. The candidate(s) will develop and map algorithms for decoding 3D streaming data on VSP. Subsequently, the candidate(s) will research, develop, and map algorithms for 3D viewpoint interpolation, occlusion decoding, and 3D rendering. In the course of the project, the candidates will propose and implement additions to VSP, in order to efficiently support the new algorithms.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering, Computer Engineering, or Computing Science, with an analytical mind and skilled in algorithm development and implementation in C/C++.
Location: Eindhoven
Start date: as soon as possible
Duration: 6 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
- CODE: CE2010-03
Title: Image Signal Processing for Mobile Devices (MSc project)
Project Description:
Silicon Hive's HiveFlex ISP family of multi-processors is specifically targeted at image signal processing. It is currently applied in mobile phones to perform sensor image corrections, white balance correction, gamma correction, dead-pixel elimination, etc. Silicon Hive is interested in extending its ISP processors with specific features, currently found in some digital still cameras, for example red-eye reduction and smile detection, lense correction, extended depth-of-field, contrast improvement, sharpening, etc.
In order to added these features to the portfolio, teams of experts, both in Japan and in The Netherlands are working on selecting and improving algorithms, mapping them onto Silicon Hive's ISP platform, and developing extensions to ISP (accelerators, new processor instructions, new on-chip interconnect, etc.). In addition, Silicon Hive participates in several international projects on similar topics.
The candidate(s) will analyze the architecture of the existing ISP processor. The candidate(s) will research, develop, and map algorithms for digital still camera applications, as mentioned above. In the course of the project, the candidates will propose and implement additions to ISP, in order to efficiently support the new algorithms. Silicon Hive provides a camera module with image sensor and LCD display, and FPGA, in order to experiment with and validate the final solution.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering, Computer Engineering, or Computing Science, with an analytical mind and skilled in algorithm development and implementation in C/C++.
Location: Eindhoven
Start date: as soon as possible
Duration: 9 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
- CODE: CE2010-02
Title: Signal Processing in Hearing Aids (MSc project)
Project Description:
Silicon Hive is currently involved the multiple international projects (EU and others) on developing ultra low-power processor technology for medical sensor applications. Within these projects, Silicon Hive cooperates with ST Microelectronics, Philips, Infineon, IMEC, and many others to develop chips and applications for this field.
The market for ultra low-power, patient-oriented medical devices is expected to grow rapidly over the coming years. The reasons are related to aging populations and drive towards home care. Next to the medical sensor nodes of the existing projects, hearing aids are a growing market. From a scientific and technical point of view, hearing aids are very interesting. They need to operate within very low power budgets. However, the programmable processing is becoming extremely complex, involving e.g. patient-specific signal adaptations, beam forming, communications (with each other, with MP3 players, and with mobile phones), and encryption.
Silicon Hive is interested in extending its processor portfolio into the domain of hearing aids. The assignment involves studies of the hearing aid application area and algorithms, and development of processor technology, specifically adapted to the hearing aid domain.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering, Computer Engineering, or Computing Science, with an analytical mind and skilled in algorithm development and implementation in C/C++.
Location: Eindhoven
Start date: as soon as possible
Duration: 9 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
- CODE: CE2010-01
Title: Vectorizing ANSI-C Compiler (MSc project)
Project Description:
Silicon Hive is was involved the ACOTES European project on Advanced COmpiler Technologies for Embedded Streaming. Within this project, Silicon Hive cooperated with NXP, ST Microelectronics, IBM, INRIA, and UPC (Barcelona) to develop parallel compiler technology. The student will build on top of the ACOTES results. The student will extend the state-of-the-art regarding automatically vectorizing scalar
code. In addition, the student will also study and propose specific loop-nest transformations, which are needed to efficiently vectorize scalar code. Some of these features have already been implemented in GCC4. A study of these algorithms and their applicability to the Silicon Hive compiler will be part of the assignment. One of the results of the study will be a recommendation on whether to use the GCC4 front-end in place of (or next to) Silicon Hive's proprietary front-end.
The candidate will gain understanding of parallelizing compilers, resulting in a study of relevant tools, algorithms, and flows. Goal is also to propose changes to Silicon Hive's compiler to make use of the auto-vectorization features of GCC4. Silicon Hive provides development environments for multi-processor system design. If needed, Silicon Hive can provide FPGA-based emulation devices, in order to experiment
with and validate the final solution.
Company Name: Silicon Hive BV
Company Description: Silicon Hive develops and licenses application-specific processors. Some of Silicon Hive's processors are counted among the most powerful licensable cores available today. Yet they consume very little power, in order to fit the energy budget of e.g. mobile phones, medical devices, and hearing aids. In order to achieve this power efficiency, Silicon Hive's processors are specially adapted to each application domain, are very lean, and appropriately utilize every possible type of parallelism: multi-core, multi-issue, vector, pipelined operations, and parallel custom operations. Silicon Hive's customers are large silicon manufacturers (e.g. Intel, ST-Ericsson, LSI Corp.) who incorporate these processor design modules in their chip designs.
Qualifications: Electrical Engineering, Computer Engineering, or Computing Science, with an analytical mind and skilled in algorithm development and implementation in C/C++.
Location: Eindhoven
Start date: as soon as possible
Duration: 9 months
Number of positions: 1
Comment(s): Challenges include working in a multi-disciplinary team (SW/HW development & verification, but also Marketing and Product Management) and working in a multi-cultural team (36% Dutch, 18% Indian, German, US, Chinese, etc.)
