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Journal Articles

2010
  1. A. Azevedo, B.H.H. Juurlink, A Multidimensional Software Cache for Scratchpad-Based Systems, International Journal of Embedded and Real-Time Communication Systems (IJERTCS), pp. 1-20, December 2010 (BibTeX)

  2. A. Ramirez, F. Cabarcas, B.H.H. Juurlink, M. Alvarez, F. Sanchez, A. Azevedo, C.H. Meenderinck, CB Ciobanu, S. Isaza, G. N. Gaydadjiev, The SARC Architecture, IEEE Micro, pp. 16-29, October 2010, Vol. 30, Nr. 5, ISSN: 0272-1732 (BibTeX)

2009
  1. A. Azevedo, B.H.H. Juurlink, C.H. Meenderinck, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez, M. Valero, A Highly Scalable Parallel Implementation of H.264, Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC), September 2009 (BibTeX)

  2. C.H. Meenderinck, A. Azevedo, B.H.H. Juurlink, M. Alvarez, A. Ramirez, Parallel Scalability of Video Decoders, Journal of Signal Processing Systems, pp. 173, August 2009, vol 57, issue 2, http://dx.doi.org/10.1007/s11265-008-0256-9 (BibTeX)

  3. M. Alvarez, A. Ramirez, M. Valero, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture., Avances en Sistemas e Informática, June 2009, Vol. 6, No. 1, ISSN 1657-7663 (BibTeX)

  4. D. Borodin, B.H.H. Juurlink, S. Hamdioui, S. Vassiliadis, Instruction-Level Fault Tolerance Configurability, Journal of Signal Processing Systems, pp. 89-105, October 2009, Volume 57, Number 1, ISSN 1939-8018 (Print) 1939-8115 (Online) (BibTeX)

2006
  1. G. N. Gaydadjiev, C. J. Glossner, J. Takala, S. Vassiliadis, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 2006 (BibTeX)

2005
  1. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, The CSI Multimedia Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-13, January 2005, Vol. 13, No. 1 (BibTeX)

2003
  1. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Implementation of a Streaming Execution unit, Journal of Systems Architecture, pp. 599-617, vol 49, issues 12-15, December 2003, Elsevier (BibTeX)

2002
  1. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Architectural support for 3D graphics in the complex streamed instruction set, International Journal of Parallel and Distributed Systems and Networks, pp. 185-193, Calgary, Canada, December 2002, vol. 5, number 4, ISSN 1206-2138, ACTA Press (BibTeX)

  2. C. J. Glossner, T. Raja, E. Hokenek, M. Moudgill, A Multithreaded Processor Architecture for SDR, Proceedings of the Korean Institute of Communication Sciences, pp. 70-85, November 2002, Vol. 19, No. 11 (BibTeX)

1996
  1. M. Moudgill, S. Vassiliadis, Precise Interrupts, IEEE Micro, Vol 16, no 1, pp. 58-67, January 1996 (BibTeX)

1995
  1. W. Chu, S. Vassiliadis, The multi-associative branch target buffer: a cost effective BTB mechanism, Microprocessing and Microprogramming 3(41), pp. 211-225, June 1995 (BibTeX)

1994
  1. S. Vassiliadis, B. Blaner, R. J. Eickermeyer, SCISM: A Scalable Compound Instruction Set Machine, IBM Journal of Research and Development, Vol. 38, No. 1, pp. 59-78, January 1994 (BibTeX)

Conference Papers

2011
  1. A. Azevedo, B.H.H. Juurlink, An Instruction to Accelerate Software Caches, To appear in the Proceedings of the 2011 Conference on Architecture of Computing Systems (ARCS 2011), Como, Italy, February 2011 (BibTeX)

2010
  1. M Briejer, C.H. Meenderinck, B.H.H. Juurlink, Extending the Cell SPE with Energy Efficient Branch Prediction, Proceedings Euro-Par Conference, September 2010 (BibTeX)

  2. C.H. Meenderinck, B.H.H. Juurlink, A Case for Hardware Task Management Support for the StarSS Programming Model, Proceedings Conference on Digital System Design Architectures, Methods and Tools; special session on Multicore Systems: Design and Application, September 2010 (BibTeX)

  3. C.C. Chi, B.H.H. Juurlink, C.H. Meenderinck, Evaluation of Parallel H.264 Decoding Strategies for the Cell Broadband Engine, Proceedings International Conference on Supercomputing (ICS), June 2010 (BibTeX)

  4. D. Borodin, B.H.H. Juurlink, Protective Redundancy Overhead Reduction Using Instruction Vulnerability Factor, Proceedings of the ACM International Conference on Computing Frontiers, pp. 319-326, Bertinoro, Italy, May 2010 (BibTeX)

  5. D. Borodin, B.H.H. Juurlink, Instruction Precomputation with Memoization for Fault Detection, DATE-2010: Proceedings of the Design, Automation and Test in Europe, pp. 1665-1668, Dresden, Germany, March 2010 (BibTeX)

  6. A.J. van de Goor, G. N. Gaydadjiev, S. Hamdioui, Memory Testing with a RISC Microcontroller, Proceedings of Design, Automation and Test in Europe 2010 (DATE), pp. 214-119, Dresden, Germany, March 2010 (BibTeX)

  7. S. Isaza, F. Sanchez, G. N. Gaydadjiev, A. Ramirez, M. Valero, Scalability Analysis of Progressive Alignment in a Multicore, Proc. of IEEE international Workshop on Multicore Computing Systems (MuCoCoS), pp. 889-894, Krakow, Poland, February 2010 (BibTeX)

2009
  1. D. Borodin, B.H.H. Juurlink, S Kaxiras, Instruction Precomputation for Fault Detection, 12th Euromicro Conference on Digital System Design (DSD-2009), Patras, Greece, August 2009 (BibTeX)

  2. C.H. Meenderinck, B.H.H. Juurlink, Specialization of the Cell SPE for Media Applications, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, July 2009 (BibTeX)

  3. A. Azevedo, B.H.H. Juurlink, Scalar Processing Overhead on SIMD-Only Architectures, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 183-190, Boston, USA, July 2009 (BibTeX)

  4. M. Alvarez, A. Ramirez, M. Valero, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, Proceedings of the 4CCC: 4th Colombian Computing Conference, Bucaramanga, Colombia, April 2009 (BibTeX)

  5. M. Alvarez, A. Ramirez, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, M. Valero, Scalability of Macroblock-level Parallelism for H.264 Decoding, Proceedings of International Conference on Parallel and Distributed Systems (ICPADS), December 2009 (BibTeX)

  6. A. Azevedo, B.H.H. Juurlink, An Efficient Software Cache for H.264 Motion Compensation, Proceedings of IEEE International Symposium on System-on-Chip, pp. 147-150, Tampere, Finland, October 2009 (BibTeX)

  7. C.H. Meenderinck, B.H.H. Juurlink, Intra-Vector SIMD Instructions for Core Specialization, Proceedings of the IEEE International Conference on Computer Design, October 2009 (BibTeX)

  8. A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez, M. Valero, Parallel H.264 Decoding on an Embedded Multicore Processor, Proceedings of Hipeac Conference, Paphos, Cyprus, January 2009 (BibTeX)

2008
  1. D. Borodin, B.H.H. Juurlink, A Low-Cost Cache Coherence Verification Method for Snooping Systems, 11th Euromicro Conference on Digital System Design (DSD-2008), pp. 219-227, Parma, Italy, September 2008 (BibTeX)

  2. Z. Popovic, R. Giorgi, N. Puzovic, B.H.H. Juurlink, A. Azevedo, Analyzing Scalability of Deblocking Filter of H.264 via TLP exploitation in a new many-core architecture, Proc. 11th EUROMICRO Conference on Digital System Design, September 2008 (BibTeX)

  3. C.H. Meenderinck, B.H.H. Juurlink, (When) Will CMPs hit the Power Wall?, Proceedings of the Euro-Par 2008 Workshops (HPPC), Las Palmas de Gran Canaria, Spain, August 2008 (BibTeX)

  4. P. J. de Langen, B.H.H. Juurlink, Memory Copies in Multi-Level Memory Systems, Proceedings of 19th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP08), pp. 287-292, Leuven, Belgium, July 2008 (BibTeX)

  5. S. Isaza, F. Sanchez, G. N. Gaydadjiev, A. Ramirez, M. Valero, Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications, Proceedings of the 8th International Workshop SAMOS 2008, pp. 53-64, Samos, Greece, July 2008 (BibTeX)

  6. M. Pericàs, R. Chaves, G. N. Gaydadjiev, S. Vassiliadis, M. Valero, Vectorized AES core for high-throughput secure environments, proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR 08), pp. 83-94, Toulouse, France, June 2008 (BibTeX)

  7. A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, M. Alvarez, A. Ramirez, Analysis of Video Filtering on the Cell Processor, Proceedings of International Symposium on Circuits and Systems (ISCAS), pp. 488-491, May 2008 (BibTeX)

  8. A. Vitkovski, G. Kuzmanov, G. N. Gaydadjiev, Memory Organization with Multi-Pattern Parallel Accesses, proceedings of international conference on Design, Automation & Test in Europe (DATE), pp. 1420-1425, Munich, Germany, March 2008 (BibTeX)

  9. M. Alvarez, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, A. Terechko, J. Hoogerbrugge, A. Ramirez, Analyzing scalability limits of H.264 decoding due to TLP overhead, 6th HiPEAC Industrial Workshop, Paris, France, November 2008 (BibTeX)

  10. C.H. Meenderinck, A. Azevedo, M. Alvarez, B.H.H. Juurlink, A. Ramirez, Parallel Scalability of H.264, Proceedings of the first Workshop on Programmability Issues for Multi-Core Computers, Goteborg, Sweden, January 2008 (BibTeX)

2006
  1. A. Shahbahrami, B.H.H. Juurlink, S. Vassiliadis, Improving the Memory Behavior of Vertical Filtering in the Discrete Wavelet Transform, Proc. 3th ACM Int. Conf. on Computing Frontiers, pp. 253-260, Ischia, Italy, May 2006 (BibTeX)

  2. P. J. de Langen, B.H.H. Juurlink, Leakage-Aware Multiprocessor Scheduling for Low Power, Proceedings of the 20th International Parallel and Distributed Processing Symposium, Rhodos, Greece, April 2006 (BibTeX)

  3. A. Shahbahrami, B.H.H. Juurlink, S. Vassiliadis, Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File, Eighth IEEE International Symposium on Multimedia, pp. 37-46, San Diego, The USA, December 2006 (BibTeX)

2005
  1. S. Vassiliadis, L. A. Sousa, G. N. Gaydadjiev, The Midlifekicker Microarchitecture Evaluation Metric, Proceedings of the IEEE International conference on Application-Specific Systems, Architectures and Processors (ASAP05), pp. 92-97, Samos, Greece, July 2005 (BibTeX)

  2. B.H.H. Juurlink, A. Shahbahrami, S. Vassiliadis, Avoiding Data Conversions in Embedded Media Processors, Proceedings of the 20th ACM Symposium on Applied Computing, pp. 901-902, Santa Fe, New Mexico, USA, March 2005 (BibTeX)

  3. S. Suijkerbuijk, B.H.H. Juurlink, Implementing Hardware Multithreading in a VLIW Processor, Proc. 17th Int. Conf. on Parallel and Distributed Computing and Systems, pp. 674-679, Phoenix, AZ, USA, November 2005 (BibTeX)

2004
  1. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Visual Data Rectangular Memory, Proceedings of the 10th International Euro-Par Conference (Euro-Par 2004), pp. 760--767, Pisa, Italy, September 2004, LNCS 3149 (BibTeX)

  2. G. N. Gaydadjiev, S. Vassiliadis, SCISM versus IA-64 Tagging: Differences and Code Density Effects, Proceedings of 10th International Euro-Par Conference, pp. 571-577, Pisa, Italy, August 2004, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 3149 (BibTeX)

  3. B.H.H. Juurlink, P. J. de Langen, Dynamic Techniques to Reduce Memory Traffic in Embedded Systems, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 192-201, Ischia, Italy, April 2004 (BibTeX)

  4. B.H.H. Juurlink, Approximating the Optimal Replacement Algorithm, Proceedings of the ACM International Conference on Computing Frontiers, pp. 313-319, Ischia, Italy, April 2004 (BibTeX)

  5. P. J. de Langen, B.H.H. Juurlink, Reducing Traffic Generated by Conflict Misses in Caches, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 235-239, Ischia, Italy, April 2004 (BibTeX)

  6. P.T. Stathis, h Cheresiz, S. Vassiliadis, B.H.H. Juurlink, Sparse Matrix Transpose Unit, 18th International Parallel and Distributed Processing Symposium (IPDPS2004), pp. ??, Santa Fe, New Mexico, USA, April 2004 (BibTeX)

2003
  1. B.H.H. Juurlink, Unified Dual Data Caches, Proceedings of the Euromicro Symposium on Digital System Design, pp. 33-40, Belek, Turkey, September 2003 (BibTeX)

  2. P.T. Stathis, S. Vassiliadis, S. D. Cotofana, D-SAB: A Sparse Matrix Benchmark Suite, Proceedings of 7th International Conference on Parallel Computing Technologies (PaCT 2003), pp. 549-554, Nizhni Novgorod, Russia, September 2003 (BibTeX)

  3. P.T. Stathis, S. Vassiliadis, S. D. Cotofana, A Hierarchical Sparse Matrix Storage Format for Vector Processors, Proceedings of IPDPS 2003, pp. 61a, Nice, France, April 2003 (BibTeX)

2002
  1. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Implementation of a streaming execution unit, Proc. DSD 2002; EUROMICRO Symposium on Digital System Design, Architectures, Methods and Tools, pp. 156-164, Dortmund, Germany, September 2002, Piscataway, NJ. USA: IEEE (BibTeX)

  2. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Performance scalability of multimedia instruction set extensions, Proc. Euro-Par 2002 Parallel processing, pp. 849-861, Padeborn, Germany, September 2002, Vol. 2400. Lecture notes in computer science. Berlin: Springer. (BibTeX)

  3. S. D. Cotofana, P.T. Stathis, S. Vassiliadis, Direct and transposed sparse matrix-vector multiplication, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems, MPCS-2002, pp. 1-9, Ischia, Italy, April 2002, The National Technological University Press, Fort Collins, Colorado, USA. (BibTeX)

  4. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Architectural support for 3D graphics in the complex streamed instruction set, Proceedings of the 14th IASTED International conference on Parallel and distributed computing and systems, PDCS-2002, pp. 536-542, Cambridge, USA, November 2002, Anaheim: ACTA Press, Best paper award in the area of processor architecture, PDCS-2002 (BibTeX)

2001
  1. B.H.H. Juurlink, h Cheresiz, S. Vassiliadis, H. A. G. Wijshoff, Implementation and Evaluation of the Complex Streamed Instruction Set, Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 73-82, Barcelona, September 2001, IEEE Computer Society, Los Alamitos,ISBN: 0-7695-1363-8 (BibTeX)

  2. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, Performance of the complex streamed instruction set on image processing kernels, Proc. 7th Int. Euro-Par Conference, pp. 678-686, Manchester, UK, August 2001, Springer, Berlin, 2001, ISBN: 3-540-42495-4 (BibTeX)

  3. B.H.H. Juurlink, I. Rieping, Performance Relevant Issues for Parallel Computation Models, PDPTA'2001: proceedings. Vol 4. International Conference on Parallel and Distributed Processing Techniques and Applications, pp. 1841-1847, Las Vegas, June 2001, ISBN: 1-892512-70-X, cat. c, Projectcode: ET01-05 (BibTeX)

  4. P.T. Stathis, S. D. Cotofana, S. Vassiliadis, Sparse Matrix Vector Multiplication Evaluation Using the BBCS scheme, Proc. of 8th Panhellenic Conference on Informatics, pp. 40-49, Nicosia, Cyprus, November 2001, ISBN: 960-14-0458-9 (BibTeX)

2000
  1. S. Vassiliadis, B.H.H. Juurlink, E. A. Hakkennes, Complex streamed instructions: introduction and initial evaluation, Proc. 26th Euromicro Conference, vol 1, pp. 400-408, Maastricht, Netherlands, September 2000, IEEE Computer Society, Los Alamitos, 2000. ISBN: 0-7695-0780-8 (BibTeX)

  2. S. D. Cotofana, B.H.H. Juurlink, S. Vassiliadis, Counter Based Superscalar Instruction Issuing, Proceedings of the 26th Euromicro Conference, vol. 1, pp. 307-315, Maastricht, The Netherlands, September 2000 (BibTeX)

  3. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, BBCS based sparse matrix-vector multiplication: initial evaluation, Proc. 16th IMACS World Congress on Scientific Computation, Applied Mathematics and Simulation, pp. 1-6, Lausanne, Switzerland, August 2000, ISBN: 3-9522075-1-9 (BibTeX)

  4. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, Block Based Compression Storage Expected Performance, Proc. 14th Int. Conf. on High Performance Computing Systems and Applications (HPC 2000), pp. 389-406, Victoria, Canada, June 2000, Kluwer Academic Publishers, ISBN: 0-7923-7617-X (BibTeX)

  5. B.H.H. Juurlink, P. Kolman, F. Meyer auf der Heide, I. Rieping, Optimal Broadcast on Parallel Locality Models, 7th International Colloquium on Structural Information and Communication Complexity, pp. 211-225, June 2000, ISBN: 1-894145-06-2 (BibTeX)

1999
  1. S. Vassiliadis, S. D. Cotofana, P.T. Stathis, Vector ISA Extension for Sprase Matrix Multiplication, Proceedings of EuroPar'99 Parallel Processing, pp. 708-715, Toulouse, France, September 1999 (BibTeX)

  2. T. L. Jeremiah, S. Vassiliadis, B. Blaner, Superscalar branch instruction processor, proceedings. Vol. 2. 12th International Conference on Control Systems and Computer Science, pp. 163-168, Bucharest, January 1999, ISBN: 973-96609-5 (BibTeX)

1998
  1. S. D. Cotofana, S. Vassiliadis, On the Design Complexity of the Issue Logic of Superscalar Machines, Proc. of 24th EUROMICRO Conf., pp. 277-284, Vasteras, Sweden, August 1998, IEEE Computer Society, ISBN: 0-8186-8646-4 (BibTeX)

  2. M. Adler, W. Dittrich, B.H.H. Juurlink, M. Kutylowski, I. Rieping, Communication-Optimal Parallel Minimum Spanning Tree Algorithms, proceedings of SPAA '98, pp. 27-36, Puerto Vallarta, Mexico, June 1998 (BibTeX)

  3. B.H.H. Juurlink, Eperimental Validation of Parallel Computation Models on the Intel Paragon, 1998 IPPS/SPDP, pp. 492-497, Orlando, FL. USA, March 1998, ISBN: 0-8186-8403-8 (BibTeX)

1996
  1. Y. Sazeides, S. Vassiliadis, J. E. Smith, The Performance Potential of Data Dependence Speculation & Collapsing, Proc. 29th Symp. On Microarchitecture MICRO-29, pp. 238-249, Paris, France, December 1996 (BibTeX)

1995
  1. M. Moudgill, S. Vassiliadis, Mechanisms for Specifying Static Speculation, Proceedings of the 21st Euromicro Conference, pp. 293-300, Como, Italy, September 1995 (BibTeX)

  2. B. Blaner, S. Vassiliadis, T. L. Jeremiah, A Branch Instruction Processor for SCISM Organizations, Proceedings of the 21st Euromicro Conference, Design of Hardware/Software Systems, pp. 285-292, Como, Italy, September 1995, ISBN 0-8186-7127-0 (BibTeX)