Publications VYZAS

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Journal Articles

2010
  1. M Duranton, S. Yehia, B De Sutter, K De Bosschere, A Cohen, B Falsafi, G. N. Gaydadjiev, M. Katevenis, O. Temam, M. Valero, The HiPEAC Vision, High Performance and Embedded Architecture and Compilation, pp. 1-56, ICT-217068, Europe, January 2010 (BibTeX)

2009
  1. C. Galuzzi, C. Gou, D.R.H. Calderón, G. N. Gaydadjiev, S. Vassiliadis, High-bandwidth Address Generation Unit, Journal of Signal Processing Systems, pp. 33-44, October 2009, vol. 57 (1) (BibTeX)

  2. H. Blume, G. N. Gaydadjiev, C. J. Glossner, Special Issue on SAMOS 2007, Journal of Signal Processing Systems, pp. 119, Springer, New York, October 2009, vol 57, nr 1 (BibTeX)

2008
  1. Z. Al-Ars, S. Hamdioui, G. N. Gaydadjiev, S. Vassiliadis, Test Set Development for Cache Memory in Modern Microprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 725-732, June 2008, Vol 16, Nr. 6 (BibTeX)

  2. I. Sourdis, J. C. Bispo, J. M.P. Cardoso, S. Vassiliadis, Regular Expression Matching in Reconfigurable Hardware, Int. Journal of Signal Processing Systems for Signal, Image, and Video Technology, Volume 51, Number 1, April 2008, Springer, Invited Paper (BibTeX)

  3. I. Sourdis, D.N. Pnevmatikatos, S. Vassiliadis, Scalable MultiGigabit Pattern Matching for Packet Inspection, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, Issue 2, pp. 156-166, February 2008, Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration (BibTeX)

  4. S Bhattacharyya, J. Takala, G. N. Gaydadjiev, Special Issue on Embedded Computing Systems for DSP, Journal of Signal Processing Systems, February 2008, Vol 50, No 2 (BibTeX)

2007
  1. G. L. Reijns, A. van Gemund, Reliability Analysis of Hierarchical Systems Using Statistical Moments, IEEE Transactions on Reliability, pp. 525-533, September 2007, Volumn 56, Number 3, ISSN 0018-9529 (BibTeX)

  2. A. Hansson, K.G.W. Goossens, A. Radulescu, Avoiding message-dependent deadlock in network-based systems on chip, In VLSI Design - Special issue on Networks-on-Chip, Hindawi Publishing Corporation, pp. Article ID 95859, 10 pages, May 2007 (BibTeX)

  3. A.M. Amory, K.G.W. Goossens, E. J. Marinissen, M. Lubaszewski, F. Moraes, Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism, In IET Computers & Digital Techniques, pp. 197-206, May 2007 (BibTeX)

  4. A. Hansson, K.G.W. Goossens, A. Radulescu, A unified approach to mapping and routing on a network on chip for both best-effort and guaranteed service traffic, In VLSI Design - Special issue on Networks-on-Chip, Hindawi Publishing Corporation, pp. Article ID 68432, 16 pages, May 2007 (BibTeX)

  5. S. Vassiliadis, I. Sourdis, FLUX Interconnection Networks on Demand, Journal of Systems Architecture, pp. 777–793, October 2007, vol. 53 (10) Elsevier, Invited Paper (BibTeX)

  6. C. Ciordas, A. Hansson, K.G.W. Goossens, T. Basten, A Monitoring-aware Network-On-Chip Design Flow, Journal of Systems Architecture, October 2007 (BibTeX)

2006
  1. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Multimedia Rectangularly Addressable Memory, IEEE Transactions on Multimedia, pp. 315--322, April 2006 (BibTeX)

  2. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoder, IEEE Transactions on Computers, pp. 1630-1639, December 2006 (BibTeX)

  3. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, S. Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs, IEEE Transactions on Computer Aided Design, pp. 2989-2996, December 2006 (BibTeX)

  4. S. Hamdioui, A.J. van de Goor, J.D Reyes, M. Rodgers, Memory test experiment: industrial results and data, IEE Proceedings of Computers and Digital Techniques, pp. 1-8, January 2006, Volume 153, Issue 1 (BibTeX)

2005
  1. S. Hamdioui, J.D Reyes, New Data-Background Sequences and Their Industrial Evaluation for Word-Oriented Random-Access Memories, IEEE trans. on computer-Aided Design of Integrated Circuits and Systems,Vol. 24, Issue 5, pp. 892-904, June 2005 (BibTeX)

  2. G. Kuzmanov, S. Vassiliadis, J.T.J. Eijndhoven, Hardwired MPEG-4 Repetitive Padding, IEEE Transactions on Multimedia, pp. 261--268, April 2005, vol. 7, issue 2 (BibTeX)

  3. G. L. Reijns, A. van Gemund, Predicting the execution times of parallel-independent programs using Pearson distributions, Parallel Computing, pp. 877-899, October 2005, Issue 31, Elsevier publishers (BibTeX)

  4. h Cheresiz, B.H.H. Juurlink, S. Vassiliadis, H. A. G. Wijshoff, The CSI Multimedia Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-13, January 2005, Vol. 13, No. 1 (BibTeX)

2004
  1. J. Nikara, S. Vassiliadis, J. Takala, P. Liuha, Multiple-Symbol Parallel Decoding for Variable Length Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 676-685, July 2004 (BibTeX)

  2. S. Hamdioui, R Wadsworth, J.D Reyes, A.J. van de Goor, Memory Fault Modeling Trends: A Case Study, Journal of Electronic Testing: Theory and Applications (JETTA), pp. 245-255, June 2004, volume: 20, Issue: 3 (BibTeX)

  3. D. Iancu, C. J. Glossner, Y. Abdelilah, S. Stanley, Software AM radio implementation, Journal of electrical engineering, pp. 273-276, June 2004 (BibTeX)

  4. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 737 - 757, May 2004, Volume: 23 , Issue: 5 (BibTeX)

  5. A.J. van de Goor, An industrial evaluation of DRAM tests, IEEE Design and test of computers, pp. 430-440, May 2004 (BibTeX)

2003
  1. D.N. Pnevmatikatos, I. Sourdis, K. Vlachos, An Efficient,Low-Cost I/O Subsystem for Network Processors, IEEE Design & Test of Computers, Vol. 20, Issue 4, pp. 56-64, July 2003, Invited Paper (BibTeX)

  2. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests, Journal of Electronic Testing: Theory and Applications, pp. 195-205, April 2003 (BibTeX)

  3. Z. Al-Ars, A.J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs, IEEE Transactions on Computers, pp. 293-309, March 2003 (BibTeX)

  4. A.J. van de Goor, I. B. S. Tlili, A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories, IEEE trans. on computers, pp. 1320-1331, October 2003, volume: 52, Issue: 10 (BibTeX)

  5. Z. Al-Ars, A.J. van de Goor, Test generation and optimization for DRAM cell defects using electrical simulation, IEEE trans. on computer-Aided Design of Integrated Circuits and Systems, pp. 1371-1384, October 2003, Volume: 22 Issue: 10 (BibTeX)

2002
  1. S. Hamdioui, A.J. van de Goor, Efficient Tests for Realistic Faults in Dual-Port Memories, IEEE transaction on Computers, pp. 460-473, May 2002, Vo. 51, No. 5 (BibTeX)

  2. S. Hamdioui, A.J. van de Goor, Thorough Tesing Any Multi-Port Memory with Linear Tests, IEEE transaction on Computer-Aided Design of Inegrated Circuits and Systems, pp. 217- 231, February 2002, Vo. 21, No. 2 (BibTeX)

Conference Papers

2010
  1. A.A.C. Brandon, I. Sourdis, G. N. Gaydadjiev, General Purpose Computing with Reconfigurable Acceleration, 20th International Conference on Field Programmable Logic and Applications (FPL), pp. 588-591, Milano, Italy, August 2010 (BibTeX)

  2. D Dave, C. Strydis, G. N. Gaydadjiev, ImpEDE: A Multidimensional Design-Space Exploration Framework for Biomedical-Implant Processors, proceedings of 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP 2010) , pp. 39-46, Rennes, France, July 2010 (BibTeX)

  3. C. Strydis, D Dave, G. N. Gaydadjiev, ImpBench Revisited: An Extended Characterization of Implant-Processor Benchmarks, proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010), pp. 126-135, Samos, Greece, July 2010 (BibTeX)

  4. Z Chang, G. N. Gaydadjiev, Mirror Routing for Satellite Networks With Cross-layer Optimization, proceedings of the International Conference on Wireless and Mobile Networks (WiMo-2010) , pp. 177-189, Ankara, Turkey, July 2010, Springer-Verlag, Berlin Heidelberg (BibTeX)

  5. A.J. van de Goor, S. Hamdioui, G. N. Gaydadjiev, Using a CISC microcontroller to test embedded memories , IEEE 13th international Symposium on Design and Diagnostic of Electronics Circuits and Systems (DDECS), pp. 261 - 266 , May 2010 (BibTeX)

  6. A.J. van de Goor, C. Jung, S. Hamdioui, G. N. Gaydadjiev, Low-cost, Customized and Flexible SRAM MBIST Engine, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 382 - 387 , Vienna, Austria, April 2010 (BibTeX)

  7. A.J. van de Goor, G. N. Gaydadjiev, S. Hamdioui, Memory Testing with a RISC Microcontroller, Proceedings of Design, Automation and Test in Europe 2010 (DATE), pp. 214-119, Dresden, Germany, March 2010 (BibTeX)

  8. S Tzilis, I. Sourdis, G. N. Gaydadjiev, Fine-grain Fault Diagnosis for FPGA Logic Blocks, Int. Conf. on Field-Programmable Technology (FPT 2010), Beijing, China, December 2010 (BibTeX)

  9. M. Taouil, S. Hamdioui, E.J. Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking, IEEE 19th Asian Test Symposium (ATS2010), Shanghai, China, December 2010 (BibTeX)

  10. M. Taouil, S. Hamdioui, J. Verbree , E. J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs, IEEE International Test Conference (ITC 2010), Austin, Texas, USA, November 2010 (BibTeX)

  11. M. Taouil, S. Hamdioui, E.J. Marinissen, Impact of Test Flows on the Cost in 3D Die-to-Wafer Stacking, First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, pp. 6, Austin, Texas, USA, November 2010 (BibTeX)

  12. C. Strydis, D Dave, Identifying Optimal Generic Processors for Biomedical Implants, proceedings of 28th IEEE International Conference on Computer Design (ICCD 2010), pp. 494-501, Amsterdam, The Netherlands, October 2010 (BibTeX)

2009
  1. B. Akesson, A. Hansson, K.G.W. Goossens, Composable resource sharing based on latency-rate servers, In Proc. Euromicro Symposium on Digital System Design (DSD), August 2009 (BibTeX)

  2. A. Molnos, K.G.W. Goossens, Conservative dynamic energy management for real-time dataflow applications mapped on multiple processors, In Proc. Euromicro Symposium on Digital System Design (DSD), August 2009 (BibTeX)

  3. B. Akesson, L. Steffens, K.G.W. Goossens, Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration, In Proc. Embedded and Real-Time Computing Systems and Applications (RTCSA), Beijing, china, August 2009 (BibTeX)

  4. M.A. Wahlah, K.G.W. Goossens, Modeling reconfiguration in a FPGA with a hardwired network on chip, Reconfigurable Architecture Workshop (RAW), May 2009 (BibTeX)

  5. M. Imran, Z. Al-Ars, G. N. Gaydadjiev, Improving Soft Error Correction Capability of 4-D Parity Codes, Electronic Digest of European Test Symposium, Sevilla, Spain, May 2009 (BibTeX)

  6. S. Hamdioui, Z. Al-Ars, Scan More with Memory Scan Test, IEEE Proc. of International Conference on Design and Technology of Integrated Systems in Nano-era, pp. 204-209, April 2009 (BibTeX)

  7. G. Kuzmanov, M. Taouil, Reconfigurable Sparse/Dense Matrix-Vector Multiplier, Proceedings of the International Conference FPT 2009, pp. 483--488, Sydney, Australia, December 2009 (BibTeX)

  8. C. van der Bok, M. Taouil, P. Afratis, I. Sourdis, The TU Delft Sudoku Solver on FPGA, Int. Conf. on Field-Programmable Technology (FPT), pp. 526-529, Sydney, Australia, December 2009, 2nd prize FPT-2009 Design Competition Award (BibTeX)

  9. A.J. van de Goor, S. Hamdioui, G. N. Gaydadjiev, Z. Al-Ars, New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults, 18th IEEE Asian Test Symposium, pp. 391-397, Taichung, Taiwan, November 2009 (BibTeX)

  10. Z. Al-Ars, S. Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories, 18th IEEE Asian Test Symposium, pp. 403-408, Taichung, Taiwan, November 2009 (BibTeX)

  11. Z. Al-Ars, S. Hamdioui, Non-Algorithmic Stress Optimization Using Simulation for DRAMs, IEEE International Design and Test Workshop, Riyadh, Saudi Arabia, November 2009 (BibTeX)

  12. B. Vermeulen, K.G.W. Goossens, A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs, Symposium on VLSI Design, Automation and Test (VLSI-DAT), January 2009 (BibTeX)

2008
  1. Z Chang, G. N. Gaydadjiev, A Hybrid Cross Layer Architecture For Wireless Protocol Stacks, IEEE International Wireless Communications and Mobile Computing Conference 2008 (IWCMC08), pp. 279-285, Crete Island, Greece, August 2008 (BibTeX)

  2. C. Strydis, G. N. Gaydadjiev, The Case for a Generic Implant Processor, 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 08), pp. 3186-3191, Vancouver, Canada, August 2008 (BibTeX)

  3. C. Strydis, C. Kachris, G. N. Gaydadjiev, ImpBench: A novel benchmark suite for biomedical, microelectronic implants, Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS VIII), pp. 86-95, Samos, Greece, July 2008 (BibTeX)

  4. M. Pericàs, R. Chaves, G. N. Gaydadjiev, S. Vassiliadis, M. Valero, Vectorized AES core for high-throughput secure environments, proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR 08), pp. 83-94, Toulouse, France, June 2008 (BibTeX)

  5. F. Pratas, G. N. Gaydadjiev, M. Berekovic, L. A. Sousa, S Kaxiras, Low Power Microarchitecture with Instruction Reuse, proceedings of Computing Frontiers 2008, pp. 149-158, Ischia, Italy, May 2008, http://doi.acm.org/10.1145/1366230.1366259 (BibTeX)

  6. Z Chang, G. N. Gaydadjiev, Cross-layer Designs Architecture for LEO Satellite Ad Hoc Network, the 6th International Conference on Wired/Wireless Internet Communications, Tampere, Finland, May 2008 (BibTeX)

  7. C. Strydis, D. Zhu, G. N. Gaydadjiev, Profiling of Symmetric-Encryption Algorithms for a Novel Biomedical-Implant Architecture, Proceedings of the ACM International Conference on Computing Frontiers (CF 08), pp. 231-240, Ischia, Italy, May 2008 (BibTeX)

  8. A van den Berg, P. Ren, E. J. Marinissen, K.G.W. Goossens, G. N. Gaydadjiev, Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism, ETS, pp. 21--26, Verbania, Italy, May 2008, isbn = 978-0-7695-3150-2 (BibTeX)

  9. C. Gou, G. Kuzmanov, G. N. Gaydadjiev, SAMS: Single-Affiliation Multiple-Stride Parallel Memory Scheme, Proceedings of MAW'08, co-located with the 2008 ACM International Conference on Computing Frontiers, pp. 359-367, Ischia, Italy, May 2008 (BibTeX)

  10. K.G.W. Goossens, M. Bennebroek, J.Y. Hur, M.A. Wahlah, Hardwired Networks on Chip in FPGAs to unify Data and Configuration Interconnects, NOCS, pp. 45--54, Newcastle, UK, April 2008, isbn = 978-0-7695-3098-7 (BibTeX)

  11. B. Vermeulen, K.G.W. Goossens, S. Umrani, Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip, NOCS, pp. 3--12, Newcastle, UK, April 2008, isbn = 978-0-7695-3098-7 (BibTeX)

  12. A. Hansson, M. Wiggers, A. Moonen, K.G.W. Goossens, M. Bekooij, Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip, NOCS, Newcastle, UK, April 2008, isbn = 978-0-7695-3098-7 (BibTeX)

  13. A. C. S. Beck, M.B. Rutzig, G. N. Gaydadjiev, L. Carro, Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications, proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 1208-1213, Munich, Germany, March 2008 (BibTeX)

  14. Z. Al-Ars, S. Hamdioui, Evaluation of SRAM Faulty Behavior Under Bit Line Coupling, proceedings of IEEE International Design and Test Workshop, December 2008 (BibTeX)

  15. S. Hamdioui, Z. Al-Ars, J Jimenez, J Calero, BIST Enhancement for Detecting Bit/Byte Write Enable Faults in SOC SRAMs, Proceedings IEEE International Conference on Signals, Circuits and Systems SCS08, November 2008 (BibTeX)

  16. S. Di Carlo, P. Prinetto, A. Scionti, Z. Al-Ars, Automating Defects Simulation and Fault Modeling for SRAMs, proceedings IEEE International High Level Design Validation and Test Workshop, November 2008 (BibTeX)

  17. C. Strydis, G. N. Gaydadjiev, Profiling of Lossless-Compression Algorithms for a Novel Biomedical-Implant Architecture, The 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pp. 109-114, Atlanta, Georgia, USA, October 2008 (BibTeX)

  18. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. Mueller, Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs, Proc. IEEE International Test Conf. (ITC 08), California, US, October 2008 (BibTeX)

  19. C. Strydis, Suitable cache organizations for a novel biomedical implant processor, The 26th IEEE International Conference on Computer Design, pp. 591-598, Lake Tahoe, California, USA, October 2008 (BibTeX)

  20. F. J. Bouwens, M. Berekovic, B De Sutter, G. N. Gaydadjiev, Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array, proceedings of HiPEAC08, pp. 66-81, Goteborg, Sweden, January 2008 (BibTeX)

2007
  1. R. Amini, E.K.A. Gill, G. N. Gaydadjiev, The Challenges of Intra-Spacecraft Wireless Data Interfacing, Proceedings of 58th International Astronautical Congress (IAC07), Hyderabad, India, September 2007 (BibTeX)

  2. Z Chang, G. N. Gaydadjiev, S. Vassiliadis, Infrastructure for Cross-Layer Designs Interaction, the 16th IEEE International Conference on Computer Communications and Networks (IC3N), pp. 19-25, Honolulu, Hawaii USA, August 2007 (BibTeX)

  3. N.T. Quach, B. Zafarifar, G. N. Gaydadjiev, Real-time FPGA-implementation for blue-sky Detection, In Proceedings of the IEEE International conference on Application-Specific Systems, Architectures and Processors (ASAP07), pp. 76-82, Montreal, Canada, July 2007, IEEE Catalog number : 07EX1703C (BibTeX)

  4. C. J. Glossner, D. Iancu, M. Moudgill, M. J. Schulte, S. Vassiliadis, Trends in Low Power Handset Software Defined Radio, proceedings of SAMOS 2007, pp. 313-321, Samos, Grece, July 2007, LNCS 4599 (BibTeX)

  5. S. Hamdioui, Z. Al-Ars, J Jimenez, J Calero, PPM Reduction on Embedded Memories in System on Chip, IEEE proceedings of European Test Symposium, pp. 85-90, Freiburg, Germany, May 2007 (BibTeX)

  6. B. Vermeulen, K.G.W. Goossens, R.V. Steeden, M. Bennebroek, Communication-centric SOC debug using transactions, In Proc. European Test Symposium (ETS), pp. 69--76, Freiburg, Germany, May 2007 (BibTeX)

  7. D. Vermoen, M. Witteman, G. N. Gaydadjiev, Reverse engineering Java Card applets using power analysis, Workshop in Information Security Theory and Practices 2007, pp. 138-149, Heraklion, Crete, Greece, May 2007, LNCS 4462, Best student paper award (BibTeX)

  8. K.G.W. Goossens, B. Vermeulen, R.V. Steeden, M. Bennebroek, Transaction-based communication-centric debug, In Proc. Intl Symposium on Networks on Chip (NOCS), pp. 195--206, May 2007 (BibTeX)

  9. A. Hansson, K.G.W. Goossens, Trade-offs in the configuration of a network on chip for multiple use-cases, In Proc. Intl Symposium on Networks on Chip (NOCS), pp. 233--242, May 2007 (BibTeX)

  10. Z. Al-Ars, S. Hamdioui, G. N. Gaydadjiev, Optimizing Test Length for Soft Faults in DRAM Devices, proceedings IEEE VLSI Test Symposium, pp. 59-66, Berkeley, CA, USA, May 2007 (BibTeX)

  11. J.W. van den Brand, C. Ciordas, T. Basten, K.G.W. Goossens, Congestion-controlled best-effort communication for networks-on-chip, In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 948-953, April 2007 (BibTeX)

  12. A. Hansson, M. Coenen, K.G.W. Goossens, Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip, In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 954--959, April 2007 (BibTeX)

  13. P. Ren, A.M. Amory, E. J. Marinissen, K.G.W. Goossens, S.K. Goel, G. N. Gaydadjiev, M. Lubaszewski, F. Moraes, Test wrapper design that allows a core to be tested via a network-on-chip or other functional interconnect, In Diagnostic Services in Networks-on-Chips workshop at Design, Automation and Test in Europe Conference and Exhibition (DATE), April 2007 (BibTeX)

  14. Z. Al-Ars, S. Hamdioui, G. N. Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices, Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 1-6, April 2007 (BibTeX)

  15. J. C. Bispo, I. Sourdis, J. M.P. Cardoso, S. Vassiliadis, Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues, Int. Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 179-190, Mangaratiba, Rio de Janiero, Brazil, March 2007, LNCS (BibTeX)

  16. F. J. Bouwens, M. Berekovic, A. Kanstein, G. N. Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array, proceedings of Int. Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 1-13, Rio de Janiero, Brazil, March 2007, LNCS 4419 (BibTeX)

  17. S. Hamdioui, Z. Al-Ars, G. N. Gaydadjiev, A.J. van de Goor, An Investigation on Capacitive Coupling in RAM Address Decoders, in IEEE proc. of International Design and Test Workshop, pp. 9-14, December 2007 (BibTeX)

  18. G. Kuzmanov, W.M. van Oijen, Floating-Point Matrix Multiplication in a Polymorphic Processor, International Conference on Field Programmable Technology (ICFPT), pp. 249--252, Kokurakita, Kitakyushu, JAPAN, December 2007 (BibTeX)

  19. Z. Al-Ars, S. Hamdioui, G. N. Gaydadjiev, Precise Identification of Memory Faults Using Electrical Simulation, IEEE proc. of International Design and Test Workshop, pp. 3-8, Cairo, Egypt, December 2007 (BibTeX)

  20. Z. Al-Ars, S. Hamdioui, Automatic Analysis of Memory Faulty Behavior in Defective Memories, Proc. IEEE International Conf. on Design and Technology of Integrated Systems in Nanoscale Era, pp. 41-46, Rabat, Morocco, November 2007 (BibTeX)

  21. A. Hansson, M. Coenen, K.G.W. Goossens, Channel trees: Reducing latency by sharing time slots in time-multiplexed networks on chip, In International Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 149-154, October 2007 (BibTeX)

  22. B. Akesson, K.G.W. Goossens, M. Ringhofer, Predator: A predictable SDRAM memory controller, In International Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 251-256, October 2007 (BibTeX)

2006
  1. S. Hamdioui, Z. Al-Ars, L. Mhamdi, G. N. Gaydadjiev, S. Vassiliadis, Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies,, IEEE proceesings of Int. Conference on Design and Test of Integrated Systems in Nanoscale Technology, pp. 216-221, Tunis, September 2006 (BibTeX)

  2. C. Ciordas, A. Hansson, K.G.W. Goossens, T. Basten, A monitoring-aware NoC design flow, In Proc. Euromicro Symposium on Digital System Design, pp. 97-104, August 2006 (BibTeX)

  3. M. Berekovic, Niggemeier, A Scalable, Multi-Thread, Multi-Issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme, SAMOS Workshop on Computer Systems Architectures Modelling and Simulation and LNCS Lecture Notes on, pp. 10, Samo, Greece, July 2006 (BibTeX)

  4. W. Fang, A.J. van Genderen, R. Ishihara, R. Vikas, N. Karaki, Y. Hiroschima, S. Inoue, T. Shimoda, J.W. Metselaar, C.I.M. Beenakker, Automated Digital Circuits Design based on Single-Grain Si TFTs Fabricated Through the micro-Czochralski (Grain Filter) Process, Proc. AM-FPD 2006 Workshop, pp. 47-50, Tokyo, Japan, July 2006 (BibTeX)

  5. G. N. Gaydadjiev, S. Vassiliadis, SAD Prefetching for MPEG4 Using Flux Caches, Proceedings of the 6th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2006), pp. 248-258, Samos, Greece, July 2006, LNCS 4017 (BibTeX)

  6. S. Vassiliadis, I. Sourdis, FLUX Networks: Interconnects on Demand, Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), pp. 160-167, Samos, Greece, July 2006 (BibTeX)

  7. M. Pastrnak, P.H.N. de With, C. Ciordas, J.V. Meerbergen, K.G.W. Goossens, Mixed adaptation and fixed-reservation oS for improving Picture Quality and Resource Usage of Multimedia (NoC) Chips, In Proc. International Symposium on Consumer Electronics (ISCE), pp. 1-6, June 2006 (BibTeX)

  8. S. Hamdioui, Z. Al-Ars, G. N. Gaydadjiev, J.D Reyes, Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies, IEEE Proc. European Test Symposium Digest of Papers, May 2006 (BibTeX)

  9. Z. Al-Ars, S. Hamdioui, G. Mueller, J Vollrath, Bitline-Coupled Precharge Faults and Their Detection in Memory Devices, IEEE Proc. European Test Symposium Digest of Papers, May 2006 (BibTeX)

  10. C. Ciordas, K.G.W. Goossens, A. Radulescu, T. Basten, NoC Monitoring: Impact on the Design Flow, In Proc. International Symposium on Circuits and Systems (ISCAS), May 2006 (BibTeX)

  11. A.M. Amory, K.G.W. Goossens, E. J. Marinissen, M. Lubaszewski, F. Moraes, Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism, In Proc. European Test Symposium (ETS), pp. 213-218, May 2006 (BibTeX)

  12. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Space of DRAM Fault Models and Corresponding Testing, IEEE Proc of Design Automation and Test in Europe, pp. 1252-1257, Munich, Germany, March 2006 (BibTeX)

  13. S. Murali, M. Coenen, A. Radulescu, K.G.W. Goossens, A Methodology for Mapping Multiple Use-Cases on to Networks on Chip, In Proc. of Design, Automation and Test Conference in Europe, pp. 118-123, Munich, Germany, March 2006 (BibTeX)

  14. F. Steenhof, H. Duque, B. Nilsson, K.G.W. Goossens, R. Peset Llopis, Networks on Chips for High-End Consumer-Electronics {TV} System Architectures, In Proc. of Design, Automation and Test Conference in Europe, pp. 148-153, Munich, Germany, March 2006 (BibTeX)

  15. X. Ru, J. Dielissen, C. Svensson, K.G.W. Goossens, Synchronous Latency-Insensitive Design in Aethereal NoC, In Future Interconnects and Network on Chip workshop at Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2006 (BibTeX)

  16. K.G.W. Goossens, Multiple Use-Cases for A Network-on-Chip Design Flow, In Future Interconnects and Network on Chip workshop at Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2006 (BibTeX)

  17. M. Rieback, G. N. Gaydadjiev, B. Crispo, R. Hofman, A. Tanenbaum, A Platform for RFID Security and Privacy Administration, Proceedings of 20-th USENIX/SAGE Large Installation System Administration conference (LISA 2006), pp. 89-102, Washington DC, USA, December 2006, Best paper award (BibTeX)

  18. S. Vassiliadis, I. Sourdis, Reconfigurable FLUX Networks, IEEE International Conference on Field Programmable Technology (FPT), pp. 81-88, December 2006 (BibTeX)

  19. J. C. Bispo, I. Sourdis, J. M.P. Cardoso, S. Vassiliadis, Regular Expression Matching for Reconfigurable Packet Inspection, IEEE International Conference on Field Programmable Technology (FPT), pp. 119-126, December 2006 (BibTeX)

  20. I. Sourdis, V. Dimopoulos, D.N. Pnevmatikatos, S. Vassiliadis, Packet Pre-filtering for Network Intrusion Detection, in 2nd ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pp. 183-192, San Jose, California, December 2006 (BibTeX)

  21. S. Vassiliadis, I. Sourdis, Reconfigurable Fabric Interconnects, in Int. Symposium on System-on-Chip (SoC), pp. 41-44, Tampere, Finland, November 2006 (BibTeX)

  22. B. R. Donchev, G. Kuzmanov, G. N. Gaydadjiev, External Memory Controller for Virtex II Pro, in Proceedings of International Symposium on System-on-Chip 2006, pp. 37--40, November 2006 (BibTeX)

  23. S. Hamdioui, Z. Al-Ars, G. N. Gaydadjiev, J.D Reyes, Comparison of Static and Dynamic Faults in 65nm Memory Technology, Proc. IEEE International Design and Test Workshop, November 2006 (BibTeX)

  24. Z. Al-Ars, S. Hamdioui, G. N. Gaydadjiev, Using Linear Tests for Transient Faults in DRAMs, Proc. IEEE International Design and Test Workshop, November 2006 (BibTeX)

  25. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, G. N. Gaydadjiev, J Vollrath, DRAM-Specific Space of Memory Tests, Proc. IEEE International Test Conference, pp. 1-10, October 2006 (BibTeX)

  26. B.G.C. de Ruijsscher, G. N. Gaydadjiev, J. Lichtenauer, E. A. Hendriks, FPGA accelerator for real-time skin segmentation, Proceedings of IEEE ESTIMedia 2006. Embedded Systems for Real Time Multimedia, pp. 93-97, Seoul, Korea, October 2006, ISBN 0-7803-9783-5 (BibTeX)

  27. C. Bartels, J. Huiskens, K.G.W. Goossens, P. Groeneveld, J.V. Meerbergen, Comparison of An Aethereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip, In Proc. IFIP International Conference on Very Large Scale Integration (VLSI-SoC),, pp. 80--85, October 2006 (BibTeX)

  28. C. Ciordas, K.G.W. Goossens, T. Basten, A. Radulescu, A. Boon, Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective, In Proc. Symposium on Industrial Embedded Systems (IES), pp. 1--10, Antibes, France, October 2006 (BibTeX)

  29. M. Coenen, S. Murali, A. Radulescu, K.G.W. Goossens, A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control, In International Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 130-135, Seoul, Korea, October 2006 (BibTeX)

  30. J.W. van de Waerdt, S. Vassiliadis, E.W. Bellers, J.G.W.M. Janssen, Motion Estimation and Temporal Up-Conversion on the TM3270 Media-Processor, Proceedings of the 16th IEEE International Conference on Consumer Electronics, pp. 315-316, January 2006 (BibTeX)

  31. S. Murali, M. Coenen, A. Radulescu, K.G.W. Goossens, Mapping and Configuration Methods for Multi-Use-Case Networks on Chips, Proc. Design Automation Conference. Asia and South Pacific (ASPDAC), pp. 146-151, Yokohama, Japan, January 2006 (BibTeX)

2005
  1. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The Molen Media Processor: Design and Evaluation, Proceedings of the International Workshop on Application Specific Processors, WASP 2005, pp. 26--33, New York Metropolitan Area, USA, September 2005 (BibTeX)

  2. J.W. van de Waerdt, S. Vassiliadis, E.W. Bellers, Temporal Video Up-Conversion on a Next-Generation Media-Processor, Proceedings of the 7th IASTED International Conference on Signal and Image Processing, pp. 434--441, August 2005 (BibTeX)

  3. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, R Wadsworth, Impact of Stresses on the Fault Coverage of Memory Tests, Proc. IEEE International Workshop on Memory Technology, Design and Testing, pp. 103-108, Taipei, Taiwan, August 2005 (BibTeX)

  4. I. Sourdis, D.N. Pnevmatikatos, S. Wong, S. Vassiliadis, A Reconfigurable Perfect-Hashing Scheme for Packet Inspection, proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp. 644-647, Tampere, Finland, August 2005 (BibTeX)

  5. A. Shahbahrami, B.H.H. Juurlink, S. Vassiliadis, Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform, Proceedings of the 16th IEEE Int. Conf. on Application-Specific Systems Architectures and Processors (ASAP), pp. 393-398, Samos, Greece, July 2005 (BibTeX)

  6. J.W. van de Waerdt, S. Vassiliadis, Instruction Set Architecture Enhancements for Video Processing, Proceedings of the 16th International Conference on Application-specific Systems, Architectures and Processors, pp. 146-153, July 2005 (BibTeX)

  7. S. Vassiliadis, L. A. Sousa, G. N. Gaydadjiev, The Midlifekicker Microarchitecture Evaluation Metric, Proceedings of the IEEE International conference on Application-Specific Systems, Architectures and Processors (ASAP05), pp. 92-97, Samos, Greece, July 2005 (BibTeX)

  8. J.W. van de Waerdt, S. Vassiliadis, Instruction Set Architecture Enhancements for Video Processing, Proceedings of the 16th International Conference on Application-specific Systems, Architectures and Processors, pp. 146-153, July 2005 (BibTeX)

  9. G. N. Gaydadjiev, S. Vassiliadis, Flux Caches: What Are They and Are They Useful?, Proceedings of the 5th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2005), pp. 93-102, Samos, Greece, July 2005, LNCS 3553 (BibTeX)

  10. C. J. Glossner, S. Dorward, S. Jinturkar, M. Moudgill, E. Hokenek, M. J. Schulte, S. Vassiliadis, Sandbridge Software Tools, Proceedings of SAMOS 05, pp. 269-278, Samos, Greece, July 2005, Springer-Verlag Lecture Notes in Computer Science (LNCS) (BibTeX)

  11. A. Shahbahrami, B.H.H. Juurlink, S. Vassiliadis, Matrix Register File and Extended Subwords: Two Techniques for Embedded Media Processors, Proceedings of the 2nd ACM Int. Conf. on Computing Frontiers, pp. 171-180, May 2005 (BibTeX)

  12. B.H.H. Juurlink, A. Shahbahrami, S. Vassiliadis, Avoiding Data Conversions in Embedded Media Processors, Proceedings of the 20th ACM Symposium on Applied Computing, pp. 901-902, Santa Fe, New Mexico, USA, March 2005 (BibTeX)

  13. J.W. van de Waerdt, J.P. van Itegem, G. Slavenburg, S. Vassiliadis, Motion Estimation Performance of the TM3270, Proceedings of the ACM Symposium on Applied Computing, pp. 850-856, March 2005 (BibTeX)

  14. Z. Al-Ars, S. Hamdioui, G. Mueller, A.J. van de Goor, Framework for Fault Analysis and Test Generation in DRAMs, Proc. Design, Automation and Test in Europe, pp. 1020-­1021, Munich, Germany, March 2005 (BibTeX)

  15. A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Compositional memory systems for multimedia communicating tasks, Proceedings of 2005 Design, Automation and Test in Europe (DATE 2005), pp. 932-937, Munich, Germany, March 2005 (BibTeX)

  16. Z. Al-Ars, S. Hamdioui, J Vollrath, Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach, Test Symposium, 2005. Proceedings. 14th Asian, pp. 434-439, December 2005 (BibTeX)

  17. S. Suijkerbuijk, B.H.H. Juurlink, Implementing Hardware Multithreading in a VLIW Processor, Proc. 17th Int. Conf. on Parallel and Distributed Computing and Systems, pp. 674-679, Phoenix, AZ, USA, November 2005 (BibTeX)

  18. J.W. van de Waerdt, S. Vassiliadis, N. Engin, The TM3270 media-processor, MICRO 05: Proceedings of the 38th International Symposium on Microarchitecture, pp. 331-342, November 2005 (BibTeX)

  19. J.W. van de Waerdt, S. Vassiliadis, N. Engin, The TM3270 media-processor, MICRO 05: Proceedings of the 38th International Symposium on Microarchitecture, pp. 331-342, November 2005 (BibTeX)

  20. J.W. van de Waerdt, S. Vassiliadis, J.P. van Itegem, H. van Antwerpen, The TM3270 Media-Processor Data Cache, Proceedings of the IEEE International Conference on Computer Design, pp. 334--341, October 2005 (BibTeX)

  21. J.W. van de Waerdt, S. Vassiliadis, J.P. van Itegem, H. van Antwerpen, The TM3270 Media-Processor Data Cache, Proceedings of the IEEE International Conference on Computer Design, pp. 334--341, October 2005 (BibTeX)

2004
  1. S. Jintukar, C. J. Glossner, V. Kotlyar, M. Moudgill, The Sandblaster automatic mulithtreaded vectorizing compiler, Proceedings International Signal Processing Conference, pp. 1-17, September 2004 (BibTeX)

  2. Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor, Influence of Bit Line Twisting on the Faulty Behavior of DRAMs, Records IEEE International Workshop on Memory Technology, Design and Testing, pp. 32-37, San Jose, CA, August 2004 (BibTeX)

  3. A.J. van de Goor, S. Hamdioui, Z. Al-Ars, The Effectiveness of Scan Test and Its New Variants, Records IEEE International Workshop on Memory Technology, Design and Testing, pp. 26-31, San Jose, CA, August 2004 (BibTeX)

  4. S. Hamdioui, G. N. Gaydadjiev, A.J. van de Goor, The State-of-the-art and Future Trends in Testing Embedded Memories, Records IEEE International Workshop on Memory Technology, Design, and Testing, pp. 54-59, San Jose, CA, August 2004 (BibTeX)

  5. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Scene Management Models and Overlap Tests for Tile-Based Rendering, Proceedings of the EUROMICRO Symposium on Digital System Design, 2004 (DSD 2004)., pp. 424 - 431, Rennes, FRANCE, August 2004 (BibTeX)

  6. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, Logic-Enhanced Memory for 3D Graphics Tile-Based Rasterizers, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), pp. II-237 - II-240, Hiroshima, Japan, July 2004 (BibTeX)

  7. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Memory Bandwidth Requirements of Tile-Based Rendering, Proceedings of the Third and Fourth International Workshops SAMOS 2003 and SAMOS 2004 (LNCS 3133), pp. 323-332, Samos, Greece, July 2004 (BibTeX)

  8. E Surducan, D. Iancu, C. J. Glossner, Modified printed dipole antennas for wireless multi band communication devices, Proceedings of the Int. Symposium on Electromagnetic Theory, pp. 1161-1163, Pisa, Italy, July 2004 (BibTeX)

  9. L. Mhamdi, M. Hamdi, Scheduling Multicast Traffic in Internally Buffered Crossbar Switches, IEEE International Conference on Communications, (ICC 04), pp. 1103 - 1107, Paris, France, June 2004, Vol. 02 (BibTeX)

  10. C. J. Glossner, M. Moudgill, D. Iancu, The sandbridge SDR Communications platform, Proceedings IEEE Symposium joint IST workshop on mobile future and symposium on trends in communications, pp. 1-8, Piscataway, June 2004 (BibTeX)

  11. A.J. van de Goor, S. Hamdioui, Z. Al-Ars, Tests for Address Decoder Delay Faults in RAMs Due to Inter-Gate Opens, Proceedings of IEEE European Test Symposium, pp. 146-151, Corsica, France, May 2004 (BibTeX)

  12. B.H.H. Juurlink, P. J. de Langen, Dynamic Techniques to Reduce Memory Traffic in Embedded Systems, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 192-201, Ischia, Italy, April 2004 (BibTeX)

  13. P. J. de Langen, B.H.H. Juurlink, Reducing Traffic Generated by Conflict Misses in Caches, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 235-239, Ischia, Italy, April 2004 (BibTeX)

  14. B.H.H. Juurlink, Approximating the Optimal Replacement Algorithm, Proceedings of the ACM International Conference on Computing Frontiers, pp. 313-319, Ischia, Italy, April 2004 (BibTeX)

  15. P.T. Groen, P. Hamalainen, B.H.H. Juurlink, T. Hamalainen, Accelerating the Secure Remote Password Protocol Using Reconfigurable Hardware, Proceedings of the ACM International Conference on Computing Frontiers, pp. 471-480, Ischia, Italy, April 2004 (BibTeX)

  16. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, Effects of Bit Line Coupling on the Faulty Behavior of DRAMs, Proceedings IEEE VLSI Test Symposium, pp. 117-122, Napa, CA, April 2004 (BibTeX)

  17. I. Sourdis, D.N. Pnevmatikatos, Pre-decoded CAMs for Efficient and High-Speed NIDS Pattern Matching, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 258-267, Napa CA, USA, April 2004 (BibTeX)

  18. M. J. Schulte, C. J. Glossner, S Mamidi, M. Moudgill, S. Vassiliadis, A low power multithreaded processor for baseband communication systems, Proceedings SAMOS workshop 2003-2004, pp. 393-402, March 2004 (BibTeX)

  19. M. J. Schulte, Chirca, C. J. Glossner, H Wang, S Mamidi, P.I. Balzola, S. Vassiliadis, A low power carry skip adder with fast saturation, Proceedings IEEE Int. Conf.on application specific systems, architectures and processors, pp. 269-279, March 2004 (BibTeX)

  20. A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J. T. J. van Eijndhoven, Compositional Memory Systems for Data Intensive Applications, Proceedings of Design, Automation and Test in Europe 2004 (DATE'04), pp. 728-729, Paris, France, February 2004 (BibTeX)

  21. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, GRAAL - A Development Framework for Embedded Graphics Accelerators, Proceedings of Design, Automation and Test in Europe (DATE'04), pp. 1366-1367, Paris, France, February 2004 (BibTeX)

  22. Z. Al-Ars, A.J. van de Goor, Soft Faults and the Importance of Stresses in Memory Testing, Proceedings Design, Automation and Test in Europe, pp. 1084-1089, Paris, France, February 2004 (BibTeX)

  23. P. Celinski, Al-Sarawi, D. Abbott, S. D. Cotofana, S. Vassiliadis, Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach, Proceedings of the IEEE Computer Society 2004 Annual Symposium on VLSY, pp. 127-132, Louisiana, USA, February 2004 (BibTeX)

  24. D. Iancu, H. Ye, Y. Abdelilah, S Emanoil, C. J. Glossner, On the performance of multiple OFDM receivers for DVB, Proceedings IEEE Symposium joint IST workshop on mobile future and symposium on trends in communications, pp. 1-4, Slovakia, December 2004 (BibTeX)

  25. S. Hamdioui, J.D Reyes, Z. Al-Ars, Evaluation of Intra-Word Faults in Word-Oriented RAMs, To appear in Proceedings IEEE Asian Test Symposium, Kenting, Taiwan, November 2004 (BibTeX)

  26. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient Tile-Aware Bounding-Box Overlap Test for Tile Based Rendering, Proceedings 2004 International Symposium on System-on-Chip, pp. 165-168, Tampere, Finland, November 2004 (BibTeX)

  27. D. Iancu, C. J. Glossner, H. Ye, M. Moudgill, V. Kotlyar, Software rake receiver enhanced GPS system, Proceedings of the 2004 Software Defined Radio Technical Conference, pp. 97-105, Scottsdale, USA, November 2004 (BibTeX)

  28. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs, Lecture Notes in Computer Science (Proceedings of the Third International Workshop on Computer Systems: Architectures, Modeling and Simulation SAMOS III), pp. 168-177, Samos, Greece, November 2004 (BibTeX)

  29. D. Iancu, C. J. Glossner, M. Moudgill, Low delay spread multi-path cancellation of 3G WCDMA, Proceedings of the Winter Inter. Symposium on Information and Communication Technologies, pp. 428-433, Cancun, Mexico, November 2004 (BibTeX)

  30. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, 3D Graphics Tile-Based Systolic Scan-Conversion, Thirty-Eighth Asilomar Conference on, pp. 517 - 521, Pacific Grove, CA, USA, November 2004 (BibTeX)

  31. A.J. van de Goor, S. Hamdioui, Detecting Faults in Peripheral Circuits and an Evaluation of SRAM Tests, To appear Proc. IEEE International Test Conference, Charlotte, NC, October 2004 (BibTeX)

  32. C. J. Glossner, M. J. Schulte, M. Moudgill, D. Iancu, T. Raja, G. Nacer, S. Vassiliadis, Sandblaster low-power multithreaded SDR baseband processor, Proceedings of the 3rd workshop on Applications Specific Processors, pp. 53-58, Stockholm, Sweden, October 2004 (BibTeX)

  33. S. Jinturkar, V Ramadurai, S Shamsunder, M. Moudgill, C. J. Glossner, Software centric approach to developing wireless applications, Proceedings of the 2004 Software Defined Radio Technical Conference, pp. 169-173, Scottsdale, USA, October 2004 (BibTeX)

  34. C. J. Glossner, Chirca, M. J. Schulte, H Wang, N Nasimzada, S Wang, J Hoane, G. Nacer, S. Vassiliadis, Sandblaster low power DSP, Proceedings of the IEEE 2004 custom integrated circuits conference, pp. 575-581, Orlando, USA, January 2004 (BibTeX)

  35. S Shamsunder, C. J. Glossner, Reduced complexity software receivers for TD-SCDMA downlink, Proceedings of the International Signal Processing Conference, pp. 1-5, January 2004 (BibTeX)

2003
  1. B.H.H. Juurlink, Unified Dual Data Caches, Proceedings of the Euromicro Symposium on Digital System Design, pp. 33-40, Belek, Turkey, September 2003 (BibTeX)

  2. I. Sourdis, D.N. Pnevmatikatos, Fast, Large-Scale String Match for a 10Gbps FPGA-based Network Intrusion Detection System, proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL 2003), pp. 880-889, Lisbon, Portugal, September 2003 (BibTeX)

  3. Z. Al-Ars, S. Hamdioui, A.J. van de Goor, A Fault Primitive Based Analysis of Linked Faults in RAMs, Records of the 2003 International Workshop on Memory Technology, Design and Testing, pp. 33-39, San Jose, CA, USA, July 2003 (BibTeX)

  4. M.J. Geuzebroek, A.J. van de Goor, TPI for improving PR Fault Coverage of Boolean and Three-State Circuits, Proceedings of the eight IEEE European Test Workshop, pp. 3-8, May 2003 (BibTeX)

  5. S. Hamdioui, R Wadsworth, J.D Reyes, A.J. van de Goor, Importance of Dynamic Faults for New SRAM Technologies, Proceedings of the Eight IEEE European Test Workshop, pp. 29-34, Maastricht, The Netherlands, May 2003 (BibTeX)

  6. S. Hamdioui, A.J. van de Goor, M. Rodgers, Detecting intra-word faults in word-oriented memories, Proceedings of 21th IEEE VLSI Test Symposium, pp. 241-247, Napa Valley, CA, USA, April 2003, ISSN: 1093-0167 (BibTeX)

  7. Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter, Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation, Design, Automation and Test in Europe, pp. 484-489, Munich, Germany, March 2003 (BibTeX)

  8. Z. Al-Ars, A.J. van de Goor, Analyzing the impact of process variations on DRAM Testing, Proceedings of IEEE Asian Test Symposium, pp. 24-27, Xian, China, November 2003 (BibTeX)

  9. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, March SL: A Test For All Static Linked Memory Faults, Proceedings of IEEE Asian Test Symposium, pp. 372-377, Xi'an, China, November 2003 (BibTeX)

  10. A.J. van de Goor, Testing (embedded) memories : new fault models, test, Dft, BIST, BISR and industrial results, proceedings of eigth IEEE European Test Workshop, pp. 1, Piscataway, January 2003 (BibTeX)

  11. I. Schanstra, A.J. van de Goor, Logical and topological testing of scrambled RAMs, LATW 2003 Fourth IEEE Latin American test Workshop, pp. 66-71, January 2003 (BibTeX)

2002
  1. J. Nikara, S. Vassiliadis, J. Takala, M. Sima, P. Liuha, Parallel multiple-symbol variable-length decoding, Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 126-131, Freiburg, Germany, September 2002 (BibTeX)

  2. S. Hamdioui, A.J. van de Goor, M. Rodgers, March SS: A test for all static simple RAM faults, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), pp. 95-100, Isle of Bendor, France, July 2002 (BibTeX)

  3. E. G. Walters III, C. J. Glossner, M. J. Schulte, Automatic VHDL Model Generation of Parameterized FIR Filters, Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, pp. 1-14, July 2002 (BibTeX)

  4. M. Sima, E-J Pol, J. T. J. van Eijndhoven, S. D. Cotofana, S. Vassiliadis, Entropy Decoding on TriMedia/CPU64, Proceedings of the 2nd International Workshop on Systems, Architectures, MOdeling and Simulation (SAMOS 2002), Samos, Greece, July 2002, Leiden: SAMOS Initiative (BibTeX)

  5. S. Wong, S. D. Cotofana, On Teaching Embedded Systems Design to Electrical Engineering Students, in Proceedings of 3rd International Conference on Information Communication Technologies in Education (ICICTE2002), pp. 505-515, Samos, Greece, July 2002 (BibTeX)

  6. S. Wong, S. Vassiliadis, S. D. Cotofana, Future Directions of (Programmable and Reconfigurable) Embedded Processors, in Proceedings of the SAMOS 2002 Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, Samos, Greece, July 2002 (BibTeX)

  7. G. Kuzmanov, S. Vassiliadis, ALU Augmentation for MPEG-4 repetitive padding, MPCS'02 Proceedings of the 2002 Euromicro Conference on Massively-Parallel Computing Systems, Ischia, Italy, April 2002 (BibTeX)

  8. Z. Al-Ars, A.J. van de Goor, Approximating Infinite Dynamic Behavior for DRAM Cell Defects, IEEE VLSI Test Symposium, pp. 401-406, Monterey, CA, April 2002 (BibTeX)

  9. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 261-270, Napa Valley, California, USA, April 2002 (BibTeX)

  10. A.J. van de Goor, M.S. Abadir, J.F. Carlin, Minimal test for coupling faults in word-oriented memories, In Proceedings of Design, Automation, and Test in Europe (DATE '02), pp. 944-948, Paris, France, March 2002 (BibTeX)

  11. Z. Al-Ars, A.J. van de Goor, Modeling techniques and tests for partial faults in memory devices, Design, Automation and Test in Europe, pp. 89-93, Paris, France, March 2002 (BibTeX)

  12. Z. Al-Ars, A.J. van de Goor, DRAM Specific approximation of the faulty behavior of cell defects, Asian Test Symposium, pp. 98-103, Guam, USA, November 2002 (BibTeX)

  13. M.J. Geuzebroek, J. van der Linden, A.J. van de Goor, Test point insertion that facilitates ATPG in reducing test time and data volume, Proceedings of the International Test Conference 2002, pp. 138-148, Baltimore, USA, January 2002, I-MES-05 (BibTeX)

  14. G. Kuzmanov, S. Vassiliadis, Reconfigurable Repetitive Padding Unit, GLSVLSI '02 Proceedings of the 12th ACM Great Lakes symposium on, pp. 98-103, New York City, NY, USA, January 2002 (BibTeX)

  15. S. Hamdioui, Z. Al-Ars, A.J. van de Goor, Testing static and dynamic faults in random access memories, IEEE VLSI Test Symposium, pp. 395-400, Monterey, CA, January 2002 (BibTeX)

1987
  1. , November 1987 (BibTeX)

Patents

2010
  1. Patentnr: NL 48.293-VB, R. Amini, E.K.A. Gill, G. N. Gaydadjiev, An attitude determination system suitable for a spacecraft, December 2010 (BibTeX)

2005
  1. Patentnr: EP-1576465 A1, J. Hoogerbrugge, J.W. van de Waerdt, Counter based stride prediction table data prefetching, September 2005 (BibTeX)

  2. Patentnr: US-6760818 B2, EP-1504341 A2, J.W. van de Waerdt, Memory region based data pre-fetching, August 2005 (BibTeX)

  3. Patentnr: EP-1568036 A1, J.W. van de Waerdt, SDRAM address mapping optimized for two-dimensional accesses, August 2005 (BibTeX)

  4. Patentnr: EP-1552397 A1, P. Stravers, J.W. van de Waerdt, Iterative translation lookaside buffer, July 2005 (BibTeX)

  5. Patentnr: EP-1535163 A1, J.W. van de Waerdt, Processor prefetch to match memory bus protocol characteristics, June 2005 (BibTeX)

  6. Patentnr: EP-1546868 A1, G. Slavenburg, J.W. van de Waerdt, System and method for a fully synthesizable superpipelined VLIW processor, June 2005 (BibTeX)

  7. Patentnr: EP-1530760 A2, J.W. van de Waerdt, Instruction cache way prediction for jump targets, May 2005 (BibTeX)

  8. Patentnr: EP-1599803, R. Wester, G. Slavenburg, J.W. van de Waerdt, Reducing cache effects of certain code pieces, November 2005 (BibTeX)

2004
  1. Patentnr: US20040070525, S. Vassiliadis, J. Nikara, J. Takala, P. Liuha, Method and a system for variable length decoding and a device for the localization of codewords, April 2004 (BibTeX)

2003
  1. Patentnr: US-6643739 B2, EP-1370946 A2, J.W. van de Waerdt, P. Stravers, Cache way prediction based on instruction base register, November 2003 (BibTeX)

2002
  1. Patentnr: , E. Altman, C. J. Glossner, E. Hokenek, D. Meltzer, M. Moudgill, Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profile, US2002/0112193 A1, September 2002 (BibTeX)

  2. Patentnr: GB2365588, C. J. Glossner, E. Hokenek, M. Moudgill, System and method for arithmetic processing and program storage device therefor, February 2002 (BibTeX)

PhD Theses

2007
  1. G. N. Gaydadjiev, Testing of Modern Semiconductor Memory Structures, pp. 140, September 2007, PhD Thesis (BibTeX)

  2. I. Sourdis, Designs and Algorithms for Packet and Content Inspection, Delft, December 2007, ISBN 978-90-807957-8-5, PhD Thesis (BibTeX)

  3. R. Chaves, Secure Computing on Reconfigurable Systems, pp. 207, December 2007, PhD Thesis (BibTeX)

  4. D.R.H. Calderón, Arithmetic Soft-Core Accelerators, November 2007, PhD Thesis (BibTeX)

2005
  1. Z. Al-Ars, DRAM Fault Analysis and Test Generation, June 2005, ISBN 90-9019612-9, PhD Thesis (BibTeX)

2004
  1. J. Nikara, Application-Specific Parallel Structures for Discrete Cosine Transform and Variable Length Decoding, Tampere, Finland, June 2004, PhD Thesis (BibTeX)

2003
  1. M.J. Geuzebroek, Test Point Insertion to improve BIST performance, and to reduce ATPG test time and data volume, pp. 216, TU Delft, The Netherlands, May 2003, PhD Thesis (BibTeX)

MSc Theses

2011
  1. D. Siskos, A Co-processor for a Secure Implantable Medical Device, March 2011, MSc Thesis (BibTeX)

  2. S. Keyser, Modular RT-Motion USB, pp. 80, February 2011, CE-MS-2011-01, MSc Thesis (BibTeX)

2010
  1. A. Abi Khaled, Congestion Managment with Feedback Queue, Delft, the Netherlands, September 2010, TU Delft, CE, MSc Thesis (BibTeX)

  2. A Piplani, Stereoscopic Remote Vision System, pp. 100, August 2010, CE-MS-2010-24, MSc Thesis (BibTeX)

  3. S.H. Katamaneni, Longest Pre x Match and Incremental Updates for Range Tries, Delft, The Netherlands, August 2010, TU Delft, MSc Thesis (BibTeX)

  4. J. Verbree , On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture, On 3D Stacked IC Yield Improvement and 3D-DfT Test, July 2010, MSc Thesis (BibTeX)

  5. S Tzilis, Fine-Grain Runtime Fault Diagnosis for Reconfigurable Logic Blocks, Delft, The Netherlands, June 2010, (TU Delft), MSc Thesis (BibTeX)

  6. D. Stafylarakis, Security in RFID systems, May 2010, MSc Thesis (BibTeX)

  7. A. Noroozi, Evaluation Methodology and Systematic Selection of Microcontrollers for Delfi-n3Xt Nanosatellite, pp. 151, May 2010, CE-MS-2010-07, MSc Thesis (BibTeX)

  8. Kentie, Biological Sequence Alignment Using Graphics Processing Units, November 2010, MSc Thesis (BibTeX)

  9. D. P. Riemens, Exploring Suitable Adder Designs for Biomedical Implants, pp. 167, October 2010, MSc Thesis (BibTeX)

2009
  1. M. Abikhaled, Code Integrity Check targeted on RISC, pp. 74, September 2009, MSc Thesis (BibTeX)

  2. D. Mastenbroek, WATCH-OVER; A cooperative approach on vulnerable road user protection, August 2009, MSc Thesis (BibTeX)

  3. M.R. van der Leije, FPGA harware acceleration of co-occurring aberrations in aCHG data, August 2009, MSc Thesis (BibTeX)

  4. N.E. Cornejo, Fault Detection for the Delfi Nanosatellite Programme, pp. 116, July 2009, CE-MS-2009-12 (with distinction), MSc Thesis (BibTeX)

  5. D. Hartanto, Reliable Ground Segment Data Handling System for Delfi-n3Xt Satellite Mission, pp. 207, Delft, The Netherlands, July 2009, CE-MS-2009-14, MSc Thesis (BibTeX)

  6. G. Stefanakis, Design and Implementation of a Range Trie for Address Lookup, pp. 132, July 2009, (with distinction), MSc Thesis, cum laude (with distinction) (BibTeX)

  7. F. Lemmel, The Brandaris128 Camera, pp. 108, June 2009, CE-MS-2008-05, MSc Thesis (BibTeX)

  8. R. de Smet, Range Trie Heuristics for Variable-Size Address Region Lookup, Delft, The Netherlands, May 2009, MSc Thesis (BibTeX)

  9. W. Chim, A Flexible Electronic Paper with Integrated Display Driver using Single Grain TFT Technology, February 2009, MSc Thesis (BibTeX)

  10. Z. Ahyadi, Experimental Analysis on ECC Schemes for Fault-Tolerant Hybrid Memories, December 2009, MSc Thesis (BibTeX)

  11. K. Chandrasekar, Performance Validation of Networks on Chip, pp. 88, November 2009, CE-MS-2009-08, MSc Thesis (BibTeX)

  12. A. Thomas, IWEX Mapping on current high performance architectures, Delft, The Netherlands, October 2009, MSc Thesis (BibTeX)

2008
  1. C. Li, Testing of Deep-Submicron Embedded Memories in FPGAs, August 2008, MSc Thesis (BibTeX)

  2. S. Kootkar, Reliable Sensor Networks: A Case Study in Commuter Trains, July 2008, MSc Thesis (BibTeX)

  3. A. Arelakis, Efficient Pre-filtering Techniques for Packet Inspection, December 2008, MSc Thesis (BibTeX)

  4. GH Nazarian, On-line Testing of Routers in Networks-on-Chips, December 2008, MSc Thesis (BibTeX)

  5. D. Zhu, Profiling Symmetric Encryption Algorithms for Implantable Medical Devices, December 2008, MSc Thesis (BibTeX)

  6. F.N. Fomin, Experimental Analysis Of Design-For-Testability Techniques in SRAM, October 2008, MSc Thesis (BibTeX)

2007
  1. S. Umrani, Communication-centric Debugging of Systems on Chip using Networks on Chip, pp. 106, August 2007, MSc Thesis (BibTeX)

  2. J. Hofman, Speeding up MPEG-4 colorspace conversion, pp. 127, April 2007, MSc Thesis (BibTeX)

  3. A van den Berg, Automation of wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism in a chip, pp. 110, November 2007, MSc Thesis (BibTeX)

2006
  1. N.T. Quach, Real-time Sky-detection Implementation, pp. 119, September 2006, CE-MS-2006-04, MSc Thesis (BibTeX)

  2. J. H. Bonarius, Low Power Techniques for Computer Architectures, pp. 82, August 2006, CE-MS-2006-14, MSc Thesis (BibTeX)

  3. M. Imran, Using COTS components in space applications, pp. 115, August 2006, CE-MS-2006-09, MSc Thesis (BibTeX)

  4. F. J. Bouwens, Power and Performance Optimization for ADRES, pp. 147, August 2006, CE-MS-2006-12, MSc Thesis (BibTeX)

  5. D.C. Spitzer, A Configurable FPGA-based, Publish/Subscribe Network System, July 2006, MSc Thesis (BibTeX)

  6. D. Vermoen, Reverse engineering of Java Card applets using power analysis, pp. 84, June 2006, CE-MS-2006-05, MSc Thesis (BibTeX)

  7. B.G.C. de Ruijsscher, FPGA based accelerator for real-time skin segmentation, pp. 101, June 2006, CE-MS-2006-08, MSc Thesis (BibTeX)

  8. V. van Adrighem, Tiny Linux kernel for minimalistic embedded systems, pp. 80, April 2006, CE-MS-2006-01, MSc Thesis (BibTeX)

  9. H. J. Visser, Minimalistic Platform for Linux Enabled Embedded Systems, pp. 95, April 2006, CE-MS-2006-02, MSc Thesis (BibTeX)

  10. P. Ren, Wrapper design for the reuse of a NoC or other functional interconnect as test infrastructure, pp. 105, December 2006, CE-MS-2006-18, MSc Thesis (BibTeX)

2005
  1. Y Zhao, Benchmarking and Profiling the RSVP Protocol, August 2005, MSc Thesis (BibTeX)

  2. C. Strydis, Implantable microelectronic devices, July 2005, (with distinction), MSc Thesis (BibTeX)

  3. v/d Waal, Motion estimation algorithms with reduced memory bandwidth requirements and motion vector candidate evaluations, June 2005, MSc Thesis (BibTeX)

  4. M. Chen, H/W Architecture Design for the Publish and Subsrcibe Mechanism, Delft, The Netherlands, June 2005, MSc Thesis (BibTeX)

  5. D. Borodin, Optimisation of Multimedia Applications for the Philips Wasabi Multiprocessor System, June 2005, MSc Thesis (BibTeX)

  6. M. Ma, Developing and Implementing Phase Normalization and Peak Detection for Real-Time Image Registration, Delft, The Netherlands, June 2005, MSc Thesis (BibTeX)

  7. G. de Goede, Accelerating the XviD IDCT on DAMP, January 2005, (with distinction), MSc Thesis (BibTeX)

2004
  1. X. Li, 3D-TV Rendering on a Multiprocessor on a Chip, pp. 43, August 2004, MSc Thesis (BibTeX)

  2. M. P. Mul, PDP8 meets USB, August 2004, MSc Thesis (BibTeX)

  3. Z Chang, VoIP Jitter Buffer Algorithm Improvement for Wireless Environment, pp. 55, August 2004, MSc Thesis (BibTeX)

  4. J. van de Pol, USB-enabled PDP8 computer, pp. 99, June 2004, CE-MS-2004-04, MSc Thesis (BibTeX)

  5. J. Van der Vegt, Simulator-based exploration of the memory hierarchy for data dominated applications, pp. 84, May 2004, CE-MS-2004-01, MSc Thesis (BibTeX)

  6. P.T. Groen, Hardware Acceleration of the SRP Authentication Protocol, pp. 78, March 2004, MSc Thesis (BibTeX)

  7. S. Suijkerbuijk, Performance Evaluation of Interleaved Multithreading in VLIW Architectures, pp. 80, October 2004, MSc Thesis (BibTeX)

  8. J. Eilers, DAMP: Design of the Delft Altera-based Multimedia Platform, October 2004, CE-MS-2003-05, MSc Thesis (BibTeX)

  9. W. Zwart, TR-DAMP: Testing and redesigning the Delft Altera-based Multimedia Platform, October 2004, CE-MS-2003-06, MSc Thesis (BibTeX)

2003
  1. D. Bao Linh, Vectorization of Digital Filters for CVP, pp. 99, TU Delft, the Netherlands, July 2003, MSc Thesis (BibTeX)

  2. A. Snirpunas, Mapping of Motion Estimation on a VLIW Processor Template, Delft, The Netherlands, July 2003, MSc Thesis (BibTeX)

2002
  1. B. Zafarifar, Microcodable Discrete Wavelet Transform, August 2002, MSc Thesis (BibTeX)

 



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