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Available MSc thesis projects
This is a list of MSc topics currently available in the VYZAS context. Please contact the person in charge about the availability of the project and all additional details.
MSc
Accelerated Access To Visual Data In MPEG Context:
Recent multimedia algorithms require huge amounts of data to be transferred and processed in real-time. Examples are the motion estimation algorithms in MPEG, which require whole blocks of visual data to be accessed randomly and processed as fast as possible. While various designs of processing units, capable of handling arrays of visual data, have been proposed, feeding these units with data is still a substantial performance bottleneck. Traditionally, visual data is stored in scan-line manner in linearly addressable memories. However, in MPEG this data is processed per blocks, which are not aligned according the scan-line scheme. Hence, data reordering is required, which is a time-consuming (i.e., performance restricting) process in conventional memory organizations. To meet the MPEG requirements for high data throughput, new data memory organizations are required.
Problem statement:
Propose a hardware mechanism for solving (avoiding) the data reordering problem for accessing 2D visual. Subsequently, design the memory organization for the proposed mechanism and implement it in a cost-effective manner.
Expected effort:
The student should design a memory organization capable of accessing sub-matrices (blocks) of visual data out of 2D addressable memory buffer. The thesis should include an investigation of different memory organizations to solve the problem, a discussion of the trade-offs involved and the criteria for the final solution. A cost-effective, scalable design solution should be proposed, the choice should be well argued. More specifically, the student is expected to: 1. Make a thorough exploration of the problem and related literature and refine the initial design requirements 2. Propose (refer to) different design solutions 3. Establish criteria for design evaluation and propose a cost-effective design solution 4. Implement the design in HDL and validate it by simulations (or on an FPGA prototype chip). Preliminary simulations indicate access times for some candidate memory organizations implemented on FPGA in the range of 10-20 ns. The final output of the thesis should be a complete scalable design of memory organization implemented on platform FPGA (Xilinx VIRTEX II). Contact person: G. Kuzmanov
VLSI Design for a Single-Grain TFT technology At our university, a Single-Grain TFT technology is being developed that allows the fabrication of high-performance CMOS transistors on a TFT substrate. Advantages of this TFT technology are that circuits can be created on large, flexible materials and that also 3D circuits are possible. Currently we are working together with Bridgestone in Japan to connect their e-paper display technology with our Single-Grain TFT technology, so that we have a technology that can be used to create e.g. electronic newspapers, books, posters and price labels.
The aim of this project is to pioneer the design of VLSI circuits for the new SG TFT technology. One may e.g. think of creating a processor (an existing architecture may be used) for the SG TFT technology. Within this project, CAD tool usage, circuit design and layout design will be important.Contact person: A.J. van Genderen
Investigation of Quality of Memory Tests Context:
The area of current ASIC and microprocessor chips is dominated by on-chip memory. Product yield and reliability therefore are effectively determined by that on-chip memory. Memory tests are used to weed out and/or repair defective memories. However, the failure behavior of memories is much more complicated than that of digital logic. Therefore, in addition to the stuck-at and bridging fault models, many other fault models are being used. Industrial memory test results indicate that the established fault models do not cover all faults. Because of that, research is being performed in memory fault modeling and test design.
The recent memory tests, however, are becoming increasingly more complex in order to cover larger classes of fault models. This has reached the point where manual verification of the fault coverage is becoming impractical and/or error prone. Because of that, there is a strong need for a tool, which is able to verify whether a given set of faults is detected by a given test.
Problem statement:
Design and implement a tool, which can accept as inputs fault models and tests, and produces as output a coverage matrix for each of the tests.
Expected effort:
The student is expected to perform a literature study of current memory test verifiers, the way fault models are being specified (using fault primitives), and the way memory tests are being specified (using march, and possibly other, notation).
A flexible and extendable structure should be designed such that the simulator can be updated to cope with different memory designs (e.g., multi-port memories), new fault models and tests. The end result should be such that the established memory tests can be verified, using the current state of the art in fault modeling.
Expected effort:
The student has to design the floating-point unit and implement it in VHDL, and estimate its power consumption. Contact person: S. Hamdioui
New VLSI architecture for reconfigurable computation The purpose is to develop a VLSI architecture (at the transistor level) that allows reconfigurable computation. The architecture has similar properties as the architecture of modern FPGAs, but focusses on the the following aspects:
- fine-grain architecture; the architecture should consist of a matrix of simple elements.
- run-time partial reconfigurable; it should be possible to reconfigure parts of the total circuit during operation.
Contact person: A.J. van Genderen
Design & implementation of an ANSI C compiler for implantable microelectronic devices (index: SiMS_compiler) Context:
Within the SiMS (http://ce.et.tudelft.nl/SiMS) research framework, a novel digital architecture is currently being developed for microelectronic implantable systems. This architecture needs to be minimalistic in design to adhere to strict device requirements such as limited size, ultra-low power consumption and high reliability. It, thus, becomes the responsibility of an accompanying compiler to perform intelligent, laborious and/or necessary tasks in order to generate machine code for the SiMS architecture.
Problem statement:
The topic of this thesis (consisting of one or more projects) is, given the microarchitectural description of the SiMS digital architecture, to design the front- and back-end of a C compiler in order to generate suitable code for the SiMS machine.
Expected effort:
The student is expected, first, to perform a concise study of existing (cross-)compilers targeting low-power embedded machines such as ARM architectures and dedicated Wireless-Sensor-Network (WSN) architectures (ASIPs, ASSPs etc.). In so doing, (s)he can get insights on implementation tricks and optimizations used in those compilers and mitigate them to our implantable-machine compiler.
Second, (s)he will study the special requirements of the SiMS case and consider out-of-the-ordinary traits the compiler is required to provide. Prominent such characteristics are: i) abstraction functionality, ii) code optimizations, and iii) reliability guarantees. A more detailed discussion on those characteristics can be found in the SiMS website under "Detailed Description", section "Compiler and design Tools".
Having collected a set of design specifications for the compiler and as the third step of the topic, the student is expected to implement the front- and back-end of the compiler, able to generate machine code from ANSI C language. Attention should be spent in designing the compiler as flexible and expandable as possible so as to support the future modification (reduction, extension) of the SiMS-machine instruction set.
As the final step of this thesis, standard C code has to be converted to binary, executable code for the SiMS architecture and its equivalence has to be verified.Contact person: C. Strydis
Design & implementation of power-aware data-compression and symmetric-encryption algorithms for implantable microelectronic devices (index: SiMS_poweraware) Context:
Within the SiMS (http://ce.et.tudelft.nl/SiMS) research framework, a novel digital architecture is currently being developed for microelectronic implantable systems. This architecture needs to be minimalistic in design to adhere to strict device requirements such as limited size, ultra-low power consumption and high reliability.
Coupled with a suitable underlying machine, the SiMS framework also requires suitable software programs in order to achieve its end functionality. Our prior profiling studies have identified compression and encryption of physiological data to be crucial and common applications for executing on the SiMS processor. An interesting, currently overseen feature of such applications is power-aware execution, that is, compression and encryption speed/efficiency dynamically regulated with respect to the power consumption of the processor.
Problem statement:
This topic consists of two or more thesis projects. It entails the augmenting of existing or the design of new compression/encryption algorithms with inherent power-aware features.
Expected effort:
A detailed study on the performance, power profile, memory footprint etc. of a large range of compression/encryption algorithms has already been conducted. Based on this work, the student is expected, first, to perform a study on the suitability of those algorithms for power-aware operation and select the most promising one.
Second, based on the previous selection process, (s)he will proceed to modify the compression/encryption algorithm to incorporate power-aware features in its design. Select, sought characteristics of the final algorithm are: i) algorithm speed/efficiency scales in a predictable way with power consumption; ii) conversely, a given power profile can be achieved by properly manipulating the added features; iii) for encryption algorithms, the security level must not be compromised by the power-aware enhancements or should, at a minimum, be predictably traded over power. Further points of interest are: i) annotation of compressed/encrypted data to pass information to the receiving end; ii) the modified algorithm is also adaptive to the application at hand, e.g. control packets should be more secure than data packets, data packets should be more compressed than control packets and so on.
Power-consumption figures may be (in)directly acquired by the underlying hardware e.g. through hardware counters, IPC or battery life but acquiring them is not the focus of the required work.
An optional (but not mandatory) goal of this work is the low-power, low-area implementation of the modified algorithm in hardware (e.g. in VHDL).Contact person: C. Strydis
Investigation of Quality of Built-In-Self Repair Algorithms for embedded memories Context:
According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatically impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modeling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. Efficient repair schemes are therefore very critical in keeping a high overall yield.
There are many published repair schemes. However, the efficiency of all such techniques are never analyzed and compared with each other using the same benchmarks. Because of that, there is a strong need for a tool, which is able to verify the effectiveness of all existing repair schemes using the same benchmarks.
Problem statement:
Design (together with a PhD student) the specifications of the tool (inputs, outputs, data structures, etc). The tool should be able to accept repair algorithms and benchmarks (i.e., defective memory arrays) as inputs and produce as output the efficiency of the repair algorithm. The tool has to be implemented and evaluated.
Expected effort:
The student is expected to perform a literature study of current memory repair algorithms. The student, together with a PhD student (and may be another master student), should be able to set up the specification of the tool, implement it and validate it.Contact person: S. Hamdioui
Design of functional units for multimedia and telecommunication applications Multimedia and telecommunication applications have particular computational needs to be satisfied under real-time constraints and with low power consumption. To perform such tasks, applications may use a large variety of hardware resources spanning from microprocessors and digital signal processors to specialized functional units. For example, to improve performance and fulfill the multimedia application requirements, recent general purpose microprocessors for workstations and personal computers use special built-in hardware. In this MS project we intend to select some computations that are specific to telecommunication and multimedia applications, e.g., DCT, Huffman encoding, motion estimation, etc., and design functional units to perform such tasks. High performance as well as low power consumption are the main envisaged design constraints. We plan to follow the entire design trajectory from algorithm to layout. The project will imply, apart of the chip design (from VHDL to layout), research effort on improved algorithms and organizations for the selected tasks.Contact person: G. N. Gaydadjiev
Acceleration of CAD Tools using FPGAs Dedicated hardware may be used to accelerate several algorithms within CAD tools:
Simulators
Layout-to-circuit extractors
Placement and routing tools
Finite-Element based programs
An FPGA allows to configure - in a flexible way - this kind of hardware when a CAD tool is started The project should find out which hardware accelerations are useful, how it can done, and it should provide a prototype.
Contact person: A.J. van Genderen
Evaluating Power Management Techniques using Sleep-transistors Sleep transistors are used in low-power circuits to shut-down inactive parts of the circuit.
Within the NEMSIC project we are studying the effect of using a NEM (Nano Electro Mechanical) transistor instead of a conventional CMOS transistor as a sleep transistor.
For the above, we need benchmark circuits, including an appropriate simulation environment.
This project should result in:
- One or more appropriate benchmark circuits (e.g. a wireless sensor node).
- A simulation environment to measure power usage.
Contact person: A.J. van Genderen
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