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Journal Articles

2010
  1. M Duranton, S. Yehia, B De Sutter, K De Bosschere, A Cohen, B Falsafi, G. N. Gaydadjiev, M. Katevenis, O. Temam, M. Valero, The HiPEAC Vision, High Performance and Embedded Architecture and Compilation, pp. 1-56, ICT-217068, Europe, January 2010 (BibTeX)

2008
  1. F. Martorell, S. D. Cotofana, A. Rubio, An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates, IEEE Transactions on Nanotechnology, pp. 24-33, January 2008, Vol. 7, No. 1 (BibTeX)

2007
  1. C.H. Meenderinck, S. D. Cotofana, Computing Division Using Single-Electron Tunneling Technology, IEEE Transactions on Nanotechnology, pp. 451-459, July 2007, Vol. 6, No. 4 (BibTeX)

  2. C.H. Meenderinck, S. D. Cotofana, An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology, Romanian Journal of Information Science and Technology, pp. 67-83, March 2007, Volume 10, number 1 (BibTeX)

2006
  1. T. Niculiu, S. D. Cotofana, Hierarchical Continuous Intelligence Simulation, Romanian Journal of Information Science and Technology, pp. 201–216, September 2006 (BibTeX)

2005
  1. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, Addition Related Arithmetic Operations via Controlled Transport of Charge, IEEE Transactions on Computers, pp. 243-256, March 2005, Vol. 54, No. 3 (BibTeX)

2004
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Single Electron Encoded Latches and Flip-Flops, IEEE Transactions on Nanotechnology, pp. 237-248, June 2004, Vol. 3, No. 2, (BibTeX)

  2. C. Hu, S. D. Cotofana, J. Jianfei, Q. Cai, Analog-to-Digital Converter Based on Single-Electron Tunneling Transistors, IEEE Transactions on VLSI Systems, pp. 1209-1213, November 2004, Vol. 12, No. 11 (BibTeX)

  3. C. Hu, S. D. Cotofana, J. Jianfei, Single-Electron Tunneling Transistor Implementation of Periodic Symmetric Functions, IEEE Transactions on Circuits and Systems II, pp. 593 - 597, November 2004, Vol. 51, No.11, (BibTeX)

  4. C. Hu, S. D. Cotofana, J. Jianfei, Digital to analogue converter based on single-electron tunnelling transistor, IEE Proceedings: Circuits, Devices and Systems, pp. 438- 442, October 2004, Vol. 151, No. 5 (BibTeX)

  5. T. Niculiu, C. Aktouf, S. D. Cotofana, Hierarchical Testability Assisted Intelligent Simulation, International Journal of Modelling and Simulation, pp. 26-35, January 2004, vol. 24, nr. 1 (BibTeX)

2003
  1. L. Neuberg, K.L.M. Bertels, Heterogeneous Trading Agents, Complexity, pp. 28-35, Wiley, May 2003 (BibTeX)

  2. T. Niculiu, S. D. Cotofana, Hierarchical Templates for Simulated Intelligence, Simulation News Europe, pp. 16-22, December 2003, issue 38/39 (BibTeX)

2001
  1. T. Niculiu, C. Aktouf, S. D. Cotofana, MultiHierarchical Intelligent Simulation, "Politehnica" University of Bucharest Scientific Buletin, pp. 15-24, August 2001, C, vol. 63, nr. 3-4 (BibTeX)

  2. K.L.M. Bertels, L. Neuberg, S. Vassiliadis, G. G. Pechanek, On chaos and neural networks: the backpropagation paradigm., Artificial Intelligence Review, pp. 165-187, January 2001, ISSN: 0269-2821, cat. b, Projectcode: ET01-05. (BibTeX)

2000
  1. K.L.M. Bertels, L. Neuberg, S. Vassiliadis, G. G. Pechanek, Chaos and Neural Network Learning. Some observations, Neural Processing Letters, vol. 1998, no. 2, pp. 69-80, August 2000, ISSN: 1370-4621 (BibTeX)

  2. K.L.M. Bertels, L. Neuberg, S. Vassiliadis, G. G. Pechanek, A look inside the learning process of neural networks, Complexity, pp. 34-38, January 2000, ISSN: 1076-2787, cat. b, Projectcode: ET01-05. (BibTeX)

1998
  1. S. D. Cotofana, S. Vassiliadis, Periodic Symmetric Functions, Serial Addition, and Multiplication with Neural Networks, IEEE Transactions on Neural Networks, vol. 9, no. 6, pp. 1118-1128, November 1998, ISSN: 1045-9227 (BibTeX)

Conference Papers

2009
  1. I.O. Agbo, S. Safiruddin, S. D. Cotofana, Implementable Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology, 9th IEEE Conference on Nanotechnology IEEE NANO 2009, pp. 450-453, Genoa, Italy, July 2009 (BibTeX)

2008
  1. S. Safiruddin, S. D. Cotofana, F. Peper, J. Lee, Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology, Procedeengs of the 8th IEEE Conference on Nanothechnology, Arlington, Texas, USA, August 2008 (BibTeX)

  2. S. Safiruddin, S. D. Cotofana, F. Peper, Single Electron Tunneling Delay Insensitive and Fluctuation Based Computation Paradigms and Circuits, Proceedings of the 2008 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 69-76, Anaheim, California, USA, June 2008 (BibTeX)

2007
  1. S. Safiruddin, S. D. Cotofana, Building Blocks for Delay-Insensitive Circuits using Single Electron Tunneling Devices, Proceedings of the 7th IEEE International Conference on Nanotechnology, pp. 704-708, Hong Kong, August 2007 (BibTeX)

  2. S. D. Cotofana, On Effective Computation with Single Electron Devices, Proceedings of the 22nd Conference on Design of Circuits and Integrated Systems (DICS2007), pp. 293-298, Sevilla, Spain, November 2007 (BibTeX)

  3. F. Martorell, S. D. Cotofana, A. Rubio, Manufacturability Issues of Redundant Nanogates, Proceedings of 2007 IEEE International Semiconductor Conference, pp. 49-52, Sinaia, Romania, October 2007 (BibTeX)

2006
  1. C.H. Meenderinck, S. D. Cotofana, Basic Building Blocks for Effective Single Electron Tunneling Technology Based Computation, Proceedings of International Semiconductor Conference (CAS2006), pp. 57-62, Sinaia, Romania, September 2006 (BibTeX)

  2. D. Milosavljevic, S. D. Cotofana, A Method to Analyze the Fault Tolerance of Molecular Quantum-Dot Cellular Automata Systems, Proceedings of International Semiconductor Conference (CAS2006), pp. 399-402, Sinaia, Romania, September 2006 (BibTeX)

  3. C.H. Meenderinck, S. D. Cotofana, Computing Division in the Electron Counting Paradigm using Single Electron Tunneling Technology, proceedings of the 6th IEEE Conference on Nanotechnology, Cincinnati, Ohio USA, July 2006 (BibTeX)

  4. C.H. Meenderinck, S. D. Cotofana, High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology, Proceedings of the 6th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2006), pp. 447-456, Samos, Greece, July 2006 (BibTeX)

  5. C.H. Meenderinck, S. D. Cotofana, Electron Counting based High-Radix Multiplication in Single Electron Tunneling Technology, Proceedings of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 4571-4574, Kos, Greece, May 2006 (BibTeX)

2005
  1. C.H. Meenderinck, S. D. Cotofana, C. R. Lageweg, High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology, Proceedings of 16th International Conference on Application-Specific Systems, Architectures and Processors, pp. 294-299, Samos, Greece, July 2005 (BibTeX)

  2. S. D. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio, CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures, Proceedings of 16th International Conference on Application-Specific Systems, Architectures and Processors, pp. 260-267, Samos, Greece, July 2005 (BibTeX)

  3. C.H. Meenderinck, C. R. Lageweg, S. D. Cotofana, Design Methodology for Single Electron Based Building Blocks, Proceedings of 2005 5th IEEE Conference on Nanotechnology, pp. (CD proceedings), Nagoya, Japan, July 2005 (BibTeX)

  4. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Buffer Design Trade-Offs for Single Electron Logic Gates, Proceedings of 2005 5th IEEE Conference on Nanotechnology, pp. (CD proceedings), Nagoya, Japan, July 2005, Best paper award (BibTeX)

2004
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Binary Multiplication Based on Single Electron Tunneling, proceedings of the 15th International Conference on Application-specific Systems, Architectures and Processors, pp. 152-166, Galveston, USA, September 2004 (BibTeX)

  2. P. Celinski, D. Abbott, S. D. Cotofana, Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic, Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2004, pp. 899 - 906, Santorini, Greece, September 2004 (BibTeX)

  3. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Binary Addition based on Single Electron Tunneling Devices, Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD proceedings), Munich, Germany, August 2004 (BibTeX)

  4. C. Hu, S. D. Cotofana, J. Jianfei, Compact Current and Current Noise Models for Single-Electron Tunneling Transistors, Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD proceedings), Munich, Germany, August 2004 (BibTeX)

  5. J. Cheng, C. Hu, S. D. Cotofana, J. Jianfei, SPICE Implementation of a Compact Single Electron Tunneling Transistor Model, Proceedings of the 2004 Fourth IEEE Conference on Nanotechnology, pp. (CD proceedings), August 2004 (BibTeX)

  6. T. Niculiu, S. D. Cotofana, Hierarchical Inteligent Simulation, Proceedings of the International Conference on System Research, Informatics and Cybernetics Volume III: Cognitive, Emotive and Ethical Aspects of Decision Making in Humans and in Artificial Inteligence, pp. 45-50, Baden-Baden, Germany, July 2004 (BibTeX)

  7. C. Hu, S. D. Cotofana, J. Jianfei, Analysis of Analog to Digital Converter Based on Single Electron Tuneling Transistors, Proceedings of 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), pp. 693-696, Vancouver, Canada, May 2004 (BibTeX)

  8. T. Niculiu, M. Ciuc, S. D. Cotofana, Hierarchical Models for Intelligent Reconfigurable Simulation, Proceedings of the 15th IASTED International Conference on Modelling and Simulation (MS 2004), pp. 350-355, Marina del Rey, CA, USA, March 2004 (BibTeX)

  9. P. Celinski, Al-Sarawi, D. Abbott, S. D. Cotofana, S. Vassiliadis, Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach, Proceedings of the IEEE Computer Society 2004 Annual Symposium on VLSY, pp. 127-132, Louisiana, USA, February 2004 (BibTeX)

  10. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Effective Computation with Nanodevices: A single Electron Tunneling Case Study, Proceedings of the 2004 International Semiconductor Conference (CAS 2004), pp. 41-50, Sinaia, Romania, October 2004, Invited Paper (BibTeX)

  11. T. Niculiu, A. Manolescu, S. D. Cotofana, Looking for Intelligent Reconfigurable Simulation, Proceedings of the European Simulation and Modelling Conference ESMc 2004, pp. 5-14, Paris, France, October 2004 (BibTeX)

2003
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Single Electron Encoded Logic Memory Elements, proceedings of 3rd IEEE International Conference on Nanotechnology, pp. 449-452, San Francisco, USA, September 2003 (BibTeX)

  2. S. D. Cotofana, C. R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge, proceedings of 16th IEEE Symposium on Computer Arithmetic, pp. 245-252, Santiago de Compostela, Spain, June 2003 (BibTeX)

  3. M. D. Padure, S. D. Cotofana, S. Vassiliadis, CMOS Implementation of Generalized Threshold Functions, Proceedings of the International Work-conference on Artificial and Natural Neural Networks (IWANN2003), pp. 65-72, Menorca, Spain, June 2003, Vol. 2687/2003 (BibTeX)

  4. T. Niculiu, S. D. Cotofana, Hierarchical Reconfigurable Simulated Intelligence Templates, IASTED International Conference on Intelligent Systems and Control, pp. 39-44, Salzburg, Austria, May 2003 (BibTeX)

  5. T. Niculiu, S. D. Cotofana, Concurrent Engineering for Intelligent Simulation, European Conference on Concurrent Engineering, pp. 95-99, Plymouth, UK, April 2003 (BibTeX)

  6. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Evaluation Methodology for Single Electron Encoded Threshold Logic Gates, proceedings of the IFIP International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC), pp. 258-262, Darmstadt, Germany, December 2003 (BibTeX)

2002
  1. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A full adder implementation using SET based linear threshold gates, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002, pp. 665-669, Dubrovnik, Croatia, September 2002 (BibTeX)

  2. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Static buffered SET based logic gates, Proceedings of the 2002 2nd IEEE Conference on Nanotechnology, pp. 491-494, August 2002 (BibTeX)

  3. M. D. Padure, S. D. Cotofana, S. Vassiliadis, High-speed hybrid threshold-Boolean logic counters, 45th International Midwest Symposium on Circuits and Systems, pp. 457-460, Tusla, Oklahoma, USA, August 2002 (BibTeX)

  4. E. Ogston, S. Vassiliadis, A peer-to-peer agent auction, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part I, pp. 151-159, Italy, July 2002 (BibTeX)

  5. T. Niculiu, S. D. Cotofana, Hierarchical Intellignet Mixed Simulation, 16th European Simulation Multiconference, pp. 159-162, Darmstadt, Germany, June 2002 (BibTeX)

  6. E. Ogston, S. Vassiliadis, Unstructured agent matchmaking: experiments in timing and fuzzy matching, Proceedings of the 2002 ACM symposium on applied computing, pp. 300-306, Madrid, Spain, March 2002 (BibTeX)

  7. P. Celinski, S. D. Cotofana, D. Abbott, Threshold Logic Parallel Counters for 32-bit Multipliers, Proc. SPIE Smart Structures, Devices and Systems, Vol. 4935, pp. 205-214, Melbourne, Australia, December 2002 (BibTeX)

  8. T. Niculiu, C. Aktouf, S. D. Cotofana, High-level intelligence-oriented simulation, CAS 2002 proceedings, Volume 2, pp. 381-385, Sinaia, November 2002 (BibTeX)

2001
  1. T. Niculiu, S. D. Cotofana, Hierarchical intelligent simulation, proceedings. 15th European Simulation Multiconference, pp. 243-246, Prague, Czech Republic, June 2001 (BibTeX)

  2. E. Ogston, S. Vassiliadis, Matchmaking among minimal agents without a facilitator, Proceedings. 5th International Conference on Autonomous Agents, pp. 608-615, Montreal, Canada, May 2001 (BibTeX)

  3. T. Niculiu, S. D. Cotofana, Multi-hierarchical learning-based co-simulation, Proceedings. IASTED International Conference: Modelling and Simulation, pp. 24-29, Pittsburg, USA, May 2001 (BibTeX)

  4. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, A linear threshold gate implementation in single electron technology, Proceedings. IEEE Computer Society Workshop on VLSI 2001: Emerging Technologies for VLSI Systems, pp. 93-98, Orlando, USA, April 2001 (BibTeX)

  5. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Achieving fanout capabilities in single electron encoded logic networks, Proceedings. Vol. 2. 6th International Conference on Solid-State and Integrated Circuit Technology, pp. 1383-1386, Shanghai, China, October 2001 (BibTeX)

  6. C. R. Lageweg, S. D. Cotofana, S. Vassiliadis, Digital to analog conversion performed in single electron technology, proceedings. 1st IEEE Conference on Nanotechnology, pp. 105-110, Maui, USA, October 2001 (BibTeX)

2000
  1. T. Niculiu, C. Aktouf, S. D. Cotofana, Hierarchical interfaces for hardware/software systems, proceedings of 14th European simulation multiconference, pp. 647-654, Ghent, Belgium, May 2000 (BibTeX)

  2. T. Niculiu, S. D. Cotofana, A. Manolescu, Hierarchical approach for hardware/software systems, 23rd International semicondutor conference CAS 2000, pp. 223-226, Sinaia, Romania, October 2000 (BibTeX)

1999
  1. K.L.M. Bertels, M. Boman, Agent-Based Social Simulation in Markets, Proceedings of the WAEC '99 Workshop on Agents in Electronic Commerce, pp. 1-9, Hong Kong, China, December 1999, S.n., S.l., cat. c, Projectcode: ET01-05 (BibTeX)

  2. T. Niculiu, S. D. Cotofana, A. Manolescu, Hierarchical mixed simulation for intelligent interfaces of microsystems, 22nd International semicondutor conference CAS 1999, pp. 515-518, Sanaia, Romania, October 1999 (BibTeX)

1998
  1. L. Neuberg, K.L.M. Bertels, A Simulated Stock Exchange Market : first results, Proceedings of 3rd Workshop on Economics with heterogeneous interactive agents, Ancona, Italy, January 1998 (BibTeX)

1997
  1. S. Balakrishnan, S. K. Nandy, A. van Gemund, Modeling multi-threaded architectures in PAMELA for real-time high performance applications, Proceedings of International Conference on Neural Networks, pp. 407 -414, Bangalore , India, December 1997, INSPEC Accession Number:5767672 (BibTeX)

1995
  1. K.L.M. Bertels, L. Neuberg, S. Vassiliadis, G. G. Pechanek, XOR and Backpropagation Learning: In and Out of the Chaos?, Proceedings ESANN '95 European Symposium on Artificial Neural Networks, pp. 69-74, Brussel, Belgium, April 1995 (BibTeX)

1991
  1. K.L.M. Bertels, Vanneste, The development of a Program Analyzer, Proceedings of the 6th. International Annual PEG Conference-Knowledge Based Environments for Teaching and Learning,, Genua, January 1991 (BibTeX)