Projects
Delay Modeling Framework for CMOS Threshold Logic circuits
Delay Modeling Framework for CMOS Threshold Logic circuits
Context:
The increasing demand for high-speed digital arithmetic in hardwired
processors have shifted the research efforts towards highly customized
alternative circuit techniques and specific computer arithmetic algorithms.
Among them, the Threshold logic (TL) paradigm has received increasingly
more attention in recent years since the basic TL gate can perform more
complex and wider functions (in terms of number of input variables)
than the usual Boolean CMOS gates. Basic CMOS Boolean gates have been
well studied and there are a wide range of delay models supported by
all commercial timing analyzers (e.g. Synopsys (TM), Candence (TM),
Mentor Graphics (TM) ). In contrast, Threshold Logic gates lack such
delay models diversity. Moreover, there is a need for a software framework
capable of rapid estimation of the critical path delay in a Threshold Logic
circuit, without relying on time-expensive circuit simulations.
Problem statement:
Develop a program capable of assisting the evaluation of the critical
path and critical path delay of an arbitrary Threshold Logic circuit.
Expected effort:
The student is expected to perform first a literature research in order
to become familiar with the subject of Threshold logic and CMOS gates delay
modelling. Second, the student should perform several benchmark circuit
simulations in order to extract Threshold Logic gate delay model parameters.
Finally, the student should develop a program capable of estimating accurately
the critical-path delay of an arbitrary Threshold Logic circuit.
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