MOLEN Publications

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Journal Articles

2010
  1. F. Duarte, S. Wong, Cache-Based Memory Copy Hardware Accelerator for Multi-Core Systems, IEEE Transactions on Computers, pp. 1494-1507, November 2010, volume 59, issue 11 (BibTeX)

  2. K.L.M. Bertels, V.M. Sima, Y. D. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, A. Michelotti, HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms, IEEE Micro, pp. 88-97, October 2010, Special Issue on European Multicore Processing Projects (BibTeX)

  3. M Duranton, S. Yehia, B De Sutter, K De Bosschere, A Cohen, B Falsafi, G. N. Gaydadjiev, M. Katevenis, O. Temam, M. Valero, The HiPEAC Vision, High Performance and Embedded Architecture and Compilation, pp. 1-56, ICT-217068, Europe, January 2010 (BibTeX)

2009
  1. C. Galuzzi, C. Gou, D.R.H. Calderón, G. N. Gaydadjiev, S. Vassiliadis, High-bandwidth Address Generation Unit, Journal of Signal Processing Systems, pp. 33-44, October 2009, vol. 57 (1) (BibTeX)

2008
  1. J.Y. Hur, S. Wong, T. P. Stefanov, Design Trade-offs in Customized On-chip Crossbar Schedulers, Journal of Signal Processing Systems (on-line), ISSN number 1939-8018, September 2008 (BibTeX)

  2. R. Chaves, G. Kuzmanov, L. A. Sousa, S. Vassiliadis, Cost-Efficient SHA Hardware Accelerators, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 999--1008, August 2008, Volume 16, Number 8, ISSN 1063-8210 (BibTeX)

  3. B.H.H. Juurlink, I. Antochi, D. Crisu, S. D. Cotofana, S. Vassiliadis, GRAAL: A Framework for Low-Power 3D Graphics Accelerators, IEEE Computer Graphics and Applications, pp. 63-73, July 2008 (BibTeX)

  4. J.Y. Hur, S. Wong, S. Vassiliadis, Partially reconfigurable point-to-point FPGA interconnects, International Journal of Electronics, vol. 95, no. 7, pp. 725-742, July 2008 (BibTeX)

  5. M. Wirthlin, D. Poznanovic, P. Sundararajan, A. Coppola, D. Pellerin, W Najjar, R. Bruce, M. Babst, O. Pritchard, G. Kuzmanov, OpenFPGA CoreLib core library interoperability effort, Parallel Computing Journal, Volume 34, Issue 4-5, pp. 231-244, May 2008, ISSN:01678191 (BibTeX)

  6. S Bhattacharyya, J. Takala, G. N. Gaydadjiev, Special Issue on Embedded Computing Systems for DSP, Journal of Signal Processing Systems, February 2008, Vol 50, No 2 (BibTeX)

2007
  1. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, The Molen Compiler for Reconfigurable Processors, ACM Transactions in Embedded Computing Systems (TECS), February 2007, Volume 6 , Issue 1 (BibTeX)

2006
  1. G. N. Gaydadjiev, C. J. Glossner, J. Takala, S. Vassiliadis, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 2006 (BibTeX)

  2. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Interprocedural Compiler Optimization for Partial Run-Time Reconguration, Journal of VLSI Signal Processing, pp. 161-172, May 2006, Volume 43, Number 2 (BibTeX)

  3. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Multimedia Rectangularly Addressable Memory, IEEE Transactions on Multimedia, pp. 315--322, April 2006 (BibTeX)

2005
  1. G. Kuzmanov, S. Vassiliadis, J.T.J. Eijndhoven, Hardwired MPEG-4 Repetitive Padding, IEEE Transactions on Multimedia, pp. 261--268, April 2005, vol. 7, issue 2 (BibTeX)

  2. M. Sima, S. D. Cotofana, J.T.J. Eijndhoven, S. Vassiliadis, L.J. Visser, IEEE-Compliant IDCT on FPGA-Augmented TriMedia, Journal of VLSI Signal Processing, pp. 195-212, March 2005, vol. 39, No. 3 (BibTeX)

2004
  1. J. Nikara, S. Vassiliadis, J. Takala, P. Liuha, Multiple-Symbol Parallel Decoding for Variable Length Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 676-685, July 2004 (BibTeX)

  2. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, L.J. Visser, Pel Reconstruction on FPGA-Augmented TriMedia, IEEE Transactions on VLSI Systems, pp. 622-635, June 2004, Vol. 12, No. 6, (BibTeX)

  3. D. Iancu, C. J. Glossner, Y. Abdelilah, S. Stanley, Software AM radio implementation, Journal of electrical engineering, pp. 273-276, June 2004 (BibTeX)

  4. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K.L.M. Bertels, G. Kuzmanov, E. Moscu Panainte, The Molen Polymorphic Processor, IEEE Transactions on Computers, pp. 1363- 1375, November 2004, Volume 53, Issue 11 (BibTeX)

2003
  1. S. Vassiliadis, S. Wong, S. D. Cotofana, Microcode Processing: Positioning and Directions, IEEE Micro, vol. 23, no. 4, pp. 21-30, July 2003 (BibTeX)

  2. C. J. Glossner, D. Iancu, J. Lu, E. Hokenek, M. Moudgill, A Software Defined Communications Baseband Design, IEEE Communications Magazine, pp. 120-128, vol.41, No. 1, January 2003 (BibTeX)

2001
  1. E. A. Hakkennes, S. Vassiliadis, Multimedia Execution Hardware Accelerator, Journal of VLSI Signal Processing Systems, 28, pp. 221-234, July 2001 (BibTeX)

2000
  1. E. A. Hakkennes, S. Vassiliadis, Multimedia execution hardware accelerator, Journal of VLSI signal processing systems for signal image and video technology, pp. 221-234, March 2000 (BibTeX)

1998
  1. C. J. Glossner, J. Thilo, S. Vassiliadis, Java Signal Processing: FFT's with Bytecodes, Journal of Concurrency and Experience, pp. 1173-1178, October 1998, vol 10, no. 11-13 (BibTeX)

Conference Papers

2011
  1. L. Zhang, K. Zhang, T.S. Chang, G. Lafruit, G. Kuzmanov, D. Verkest, Design and Implementation of Real-Time High-Definition Stereo Matching SoC on FPGA, Proceedings of the Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), pp. to appear, Monterey, California, February 2011 (BibTeX)

2010
  1. An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder, Proceedings of the International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Samos, Greece, July 2010 (BibTeX)

  2. T. Marconi, J.Y. Hur, K.L.M. Bertels, G. N. Gaydadjiev, A Novel Configuration Circuit Architecture to Speedup Reconfiguration and Relocation for Partially Reconfigurable Devices, Proceedings of IEEE Symposium on Application Specific Processors (SASP), pp. 87-92, Anaheim, CA, USA , June 2010 (BibTeX)

  3. M. Sabeghi, K.L.M. Bertels, Interfacing Operating Systems and Polymorphic Computing Platforms based on the MOLEN Programming Paradigm, Sixth Annual Workshop on the Interaction between Operating Systems and Computer Architecture in conjunction with ISCA10, pp. 30-35, Saint-Malo, France, June 2010 (BibTeX)

  4. M. Sabeghi, H. Mushtaq, K.L.M. Bertels, Runtime Multitasking Support on Reconfigurable Accelerators, First International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies held within ACM ICS 2010, pp. 54-59, Tsukuba, Japan, June 2010 (BibTeX)

  5. V. Kyovtorov, H. Kabakchiev, G. Kuzmanov, Power analysis of parallel CA-CFAR FPGA design, Proceedings of International Radar Symposium (IRS-2010), pp. 305--308, Vilnius, Lithuania, June 2010 (BibTeX)

  6. Y. Lu, T. Marconi, K.L.M. Bertels, G. N. Gaydadjiev, A Communication Aware Online Task Scheduling Algorithm for FPGA-based Partially Reconfigurable Systems, IEEE Symposium on Field-Programmable Custom Computing Machines, 2010 (FCCM 2010), pp. 65-68, Charlotte, North Carolina, USA, May 2010 (BibTeX)

  7. T. Marconi, Y. Lu, K.L.M. Bertels, G. N. Gaydadjiev, 3D Compaction: a Novel Blocking-aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices, Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), pp. 194-206, Bangkok, Thailand, March 2010 (BibTeX)

  8. M. Fazlali, A. Zakerolhosseini, G. N. Gaydadjiev, A Modified Merging Approach for Datapath Configuration Time Reduction, proceedings of the 6th International Symposium on Applied Reconfigurable Computing (ARC2010), pp. 318-328, Bangkok, Thailand, March 2010 (BibTeX)

  9. M. Fazlali, A. Zakerolhosseini, REC-BENCH: A Tool to Create Benchmark for Reconfigurable Computers, proceedings of VI Southern Programmable Logic Conference, (SPL 2010), Porto de Galinhas Bench, Brazil, March 2010 (BibTeX)

  10. T. Marconi, D. Theodoropoulos, K.L.M. Bertels, G. N. Gaydadjiev, A Novel HDL Coding Style to Reduce Power Consumption for Reconfigurable Devices, Proceedings of the International Conference on Field-Programmable Technology (FPT), pp. 295-299, Beijing, China, December 2010 (BibTeX)

  11. D. Theodoropoulos, G. Kuzmanov, G. N. Gaydadjiev, Minimalistic Architecture for Reconfigurable Audio Beamforming, Proceedings of the International Conference on Field-Programmable Technology, pp. 503-506, Beijing, China, December 2010 (BibTeX)

  12. D. Theodoropoulos, G. Kuzmanov, G. N. Gaydadjiev, A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio, Proceedings of the International Conference on ReConFigurable Computing and FPGAs, pp. 1-6, Cancun, Mexico, December 2010 (BibTeX)

  13. Y. Lu, K.L.M. Bertels, G. N. Gaydadjiev, Efficient Hardware task reuse and interrupt handling for FPGA-based partially reconfigurable systems, Proceedings of the International Conference on Field-Programmable Technology (FPT), Beijing, China, December 2010 (BibTeX)

  14. M Nadeem, S. Wong, G. Kuzmanov, Configurable, Low-power Design for Inverse Integer Transform in H.264/AVC, International Conference on Frontiers of Information Technology (FIT), Islamabad, Pakistan, December 2010 (BibTeX)

  15. H. Mushtaq, M. Sabeghi, K.L.M. Bertels, A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms, 2010 International Conference on Reconfigurable Computing, December 2010 (BibTeX)

2009
  1. L Hasan, Z. Al-Ars, An Efficient and High Performance Linear Recursive Variable Expansion Implementation of the Smith-Waterman Algorithm, 31st Annual International Conference of the IEEE EMBS, pp. 3845-3848, Minneapolis, Minnesota, USA, September 2009 (BibTeX)

  2. M. Sabeghi, V.M. Sima, K.L.M. Bertels, Compiler Assisted Runtime Task Scheduling on a Reconfigurable Computer, 19th International Conference on Field Programmable Logic and Applications (FPL09), August 2009 (BibTeX)

  3. M. Fazlali, A. Zakerolhosseini, M. Sabeghi, K.L.M. Bertels, G. N. Gaydadjiev, Data path Configuration Time Reduction for Run-time Reconfigurable Systems, proceedings of The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA09), pp. 5, Nevada,USA, July 2009 (BibTeX)

  4. P.G. Zaykov, G. Kuzmanov, G. N. Gaydadjiev, Reconfigurable Multithreading Architectures: A Survey, Proceedings of the 9th International Workshop SAMOS 2009, pp. 263-274, Samos, Greece, July 2009, LNCS 5657; ISBN: 978-3-642-03137-3 (BibTeX)

  5. D Cabrera, X. Martorell, G. N. Gaydadjiev, E Ayguade, D. Jiménez, OpenMP extensions for FPGA Accelerators, proceedings of SAMOS-IC, pp. 17-24, Samos, Greece, July 2009 (BibTeX)

  6. G. Kuzmanov, Polymorphic Architectures - from Media Processing to Supercomputing, in Proceedings of the 10th International Conference on computer Systems and Technologies (CompSysTech 09), pp. P.4-1--P.4-10, Ruse, Bulgaria, June 2009, ISSN: 1313-8936, also in ACM International Conference Proceeding Series, Vol. 433, keynote, best paper award (BibTeX)

  7. K Sigdel, M Thompson, A. D. Pimentel, C. Galuzzi, K.L.M. Bertels, System-Level Runtime Mapping Exploration of Reconfigurable Architectures, Proceedings of International conference on 16th IEEE Reconfigurable Architectures Workshop, Rome, Italy, May 2009 (BibTeX)

  8. M. Sabeghi, K.L.M. Bertels, Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach, Design, Automation and Test in Europe (DATE09), April 2009 (BibTeX)

  9. Y. Lu, T. Marconi, K.L.M. Bertels, G. N. Gaydadjiev, Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems, International Workshop on Applied Reconfigurable Computing (ARC), pp. 216-230, Karlsruhe, Germany, March 2009 (BibTeX)

  10. G. Kuzmanov, M. Taouil, Reconfigurable Sparse/Dense Matrix-Vector Multiplier, Proceedings of the International Conference FPT 2009, pp. 483--488, Sydney, Australia, December 2009 (BibTeX)

  11. T. Marconi, Y. Lu, K.L.M. Bertels, G. N. Gaydadjiev, A Novel Fast Online Placement Algorithm on 2D Partially Reconfigurable Devices, Proceedings of the International Conference on Field-Programmable Technology (FPT), pp. 296-299, Sydney, Australia, December 2009 (BibTeX)

  12. M. Fazlali, A. Zakerolhosseini, A. Shahbahrami, G. N. Gaydadjiev, High Speed Merged-datapath Design for Run-Time Reconfigurable Systems, proceedings of International Conference on Field-Programmable Technology (FPT09), pp. 339-343, The University of New South Wales Sydney, Australia, December 2009 (BibTeX)

  13. M Nadeem, S. Wong, G. Kuzmanov, A. Shabbir, A High-Throughput, Area-Efficient Hardware Accelerator for Adaptive Deblocking Filter in H.264/AVC, 7th IEEE Workshop on Embedded systems for Real-time Multimedia (ESTIMedia 2009), pp. 18-27, Grenoble, France, October 2009 (BibTeX)

2008
  1. R. Chaves, G. Kuzmanov, L. A. Sousa, On-the-fly Attestation of Reconfigurable Hardware, Proceedings of FPL 08, pp. 71--76, Heidelberg, Germany, September 2008 (BibTeX)

  2. L Hasan, Y.M. Khawaja, A. Bais, A Systolic Array Architecture for The Smith-Waterman Algorithm With High Performance Cell Design, Proceedings of IADIS European Conference on Data Mining, pp. 35-42, Amsterdam, The Netherlands, July 2008 (BibTeX)

  3. M. Pericàs, R. Chaves, G. N. Gaydadjiev, S. Vassiliadis, M. Valero, Vectorized AES core for high-throughput secure environments, proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR 08), pp. 83-94, Toulouse, France, June 2008 (BibTeX)

  4. F. Pratas, G. N. Gaydadjiev, M. Berekovic, L. A. Sousa, S Kaxiras, Low Power Microarchitecture with Instruction Reuse, proceedings of Computing Frontiers 2008, pp. 149-158, Ischia, Italy, May 2008, http://doi.acm.org/10.1145/1366230.1366259 (BibTeX)

  5. C. Gou, G. Kuzmanov, G. N. Gaydadjiev, SAMS: Single-Affiliation Multiple-Stride Parallel Memory Scheme, Proceedings of MAW'08, co-located with the 2008 ACM International Conference on Computing Frontiers, pp. 359-367, Ischia, Italy, May 2008 (BibTeX)

  6. V. Kyovtorov, H. Kabakchiev, V. Behar, G. Kuzmanov, I. Garvanov, L. Doukovska, FPGA implementation of low-frequency GPR signal algorithm using frequency stepped chirp signals in the time domain, Proceedings of International Radar Symposium, pp. 4, Wroclaw, May 2008 (BibTeX)

  7. Y. Lu, T. Marconi, G. N. Gaydadjiev, K.L.M. Bertels, R. J. Meeuws, A Self-adaptive on-line Task Placement Algorithm for Partially Reconfigurable Systems, Proceedings of the 22nd Annual International Parallel & Distributed Processing Symposium (IPDPS 2008) - RAW2008, pp. 8, Miami, Florida, USA, April 2008 (BibTeX)

  8. L Hasan, Z. Al-Ars, Accurate Profiling and Acceleration Evaluation of the Smith-Waterman Algorithm using the MOLEN Platform, Proceedings of International Conference on Applied Computing, pp. 188-194, Algarve, Portugal, April 2008 (BibTeX)

  9. T. Marconi, Y. Lu, K.L.M. Bertels, G. N. Gaydadjiev, Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems, Proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 1346-1351, Munich, Germany, March 2008 (BibTeX)

  10. Y. Lu, T. Marconi, G. N. Gaydadjiev, K.L.M. Bertels, An Efficient Algorithm for Free Resources Management on the FPGA, Proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 1095-1098, Munich, Germany, March 2008 (BibTeX)

  11. R. Chaves, G. Kuzmanov, L. A. Sousa, S. Vassiliadis, Merged Computation for Whirlpool Hashing, publication at Proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 272-275, Munich, Germany, March 2008 (BibTeX)

  12. T. Marconi, Y. Lu, K.L.M. Bertels, G. N. Gaydadjiev, Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices, Proceedings of International Workshop on Applied Reconfigurable Computing (ARC), pp. 306-311, London, UK, March 2008 (BibTeX)

  13. A. C. S. Beck, M. B. Rutzig, G. N. Gaydadjiev, L. Carro, Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems, Proceedings of International Workshop on Applied Reconfigurable Computing (ARC), pp. 111-124, London, UK, March 2008 (BibTeX)

  14. A. Vitkovski, G. Kuzmanov, G. N. Gaydadjiev, Memory Organization with Multi-Pattern Parallel Accesses, proceedings of international conference on Design, Automation & Test in Europe (DATE), pp. 1420-1425, Munich, Germany, March 2008 (BibTeX)

  15. A. C. S. Beck, M. B. Rutzig, G. N. Gaydadjiev, L. Carro, Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications, proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 1208-1213, Munich, Germany, March 2008 (BibTeX)

  16. A. Molnos, S. D. Cotofana, M.J.M. Heijligers, Compositional, dynamic cache management for embedded chip multiprocessors, Proceedings of Design, Automation and Test in Europe 2008 (DATE 08), pp. 991-996, March 2008 (BibTeX)

  17. S. Wong, T. van As, G. Brown, ρ-VEX: A Reconfigurable and Extensible Softcore VLIW Processor, International Conference on Field-Programmable Technology (ICFPT), Taipei, Taiwan, December 2008 (BibTeX)

  18. L Hasan, Z. Al-Ars, Z. Nawaz, K.L.M. Bertels, Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion, Proceedings of 3rd International Design and Test Workshop IDT08, pp. 135-140, Monastir, Tunisia, December 2008 (BibTeX)

  19. J.Y. Hur, K.G.W. Goossens, L. Mhamdi, Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit-Switched Interconnects for FPGAs, VLSI-SOC, pp. 224-229, Rhodes, Greece, October 2008 (BibTeX)

  20. F. J. Bouwens, M. Berekovic, B De Sutter, G. N. Gaydadjiev, Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array, proceedings of HiPEAC08, pp. 66-81, Goteborg, Sweden, January 2008 (BibTeX)

  21. R. Chaves, B. Donchev, G. Kuzmanov, L. A. Sousa, S. Vassiliadis, BRAM-LUT tradeoff on a Polymorphic DES Design, proceedings of HiPEAC08, pp. 55-65, Goteborg, Sweden, January 2008, (LNCS 4917) (BibTeX)

  22. M. Wirthlin, D. Poznanovic, P. Sundararajan, A. Coppola, D. Pellerin, W Najjar, R. Bruce, M. Babst, P. Palazzari, G. Kuzmanov, OpenFPGA CoreLib Core Library Interoperability Effort_, Proceedings of the Third Annual Reconfigurable Systems Summer Institute (RSSI`07), pp. 10, Urbana, Illinois, USA, January 2008 (BibTeX)

2007
  1. L Hasan, Z. Al-Ars, S. Vassiliadis, Hardware Acceleration of Sequence Alignment Algorithms - An Overview, Proceedings of Inernational Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp. 92-97, Rabat , Morocco, September 2007 (BibTeX)

  2. S.D. Breijer, F. Duarte, S. Wong, An OCM Based Shared Memory Controller For Virtex 4, Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 692--696, Amsterdam, The Netherlands, August 2007 (BibTeX)

  3. S.J. Raaijmakers, S. Wong, Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), Amsterdam, The Netherlands, August 2007 (BibTeX)

  4. F. Thoma, M. Kühnle, P. Bonnot, E. Moscu Panainte, K.L.M. Bertels, S. Goller, A. Schneider, S. Guyetant, E. Schaeler, K. Müller-Glaser, MORPHEUS: HETEROGENEOUS RECONFIGURABLE COMPUTING, Proceedings of FPL 07, pp. 409-414, Amsterdam, The Netherlands, August 2007 (BibTeX)

  5. D.R.H. Calderón, G. N. Gaydadjiev, S. Vassiliadis, Reconfigurable Universal Adder, In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 07), pp. 186-191, Montreal, Quebec, Canada, July 2007, IEEE Catalog number : 07EX1703C (BibTeX)

  6. D.R.H. Calderón, C. Galuzzi, G. N. Gaydadjiev, S. Vassiliadis, High-Bandwidth Address Generation Unit, Proceedings of the Systems Architectures Modeling and Simulation (SAMOS VII) workshop, pp. 263 - 274, July 2007 (BibTeX)

  7. J.Y. Hur, T. P. Stefanov, S. Wong, S. Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler, IEEE 18th International Conference on Application-specific Systems, Architectures and Processors (ASAP07), Montreal, Canada, July 2007 (BibTeX)

  8. C. J. Glossner, D. Iancu, M. Moudgill, M. J. Schulte, S. Vassiliadis, Trends in Low Power Handset Software Defined Radio, proceedings of SAMOS 2007, pp. 313-321, Samos, Grece, July 2007, LNCS 4599 (BibTeX)

  9. K.L.M. Bertels, G. Kuzmanov, E. Moscu Panainte, G. N. Gaydadjiev, Y. D. Yankova, V.M. Sima, K Sigdel, R. J. Meeuws, S. Vassiliadis, Profiling, Compilation, and HDL Generation within the hArtes Project, FPGAs and Reconfigurable Systems: Adaptive Heterogeneous Systems-on-Chip and European Dimensions (DATE 07 Workshop), pp. 53-62, Nice, France, April 2007 (BibTeX)

  10. J.Y. Hur, T. P. Stefanov, S. Wong, S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects, Proceedings of international workshop on applied reconfigurable computing (ARC07), In LNCS 4419, pp. 61-72, Rio de Janeiro, Brazil, March 2007 (BibTeX)

  11. J.Y. Hur, S. Wong, S. Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs, Proceedings of international workshop on applied reconfigurable computing (ARC07), In LNCS 4419, pp. 49-60, Rio de Janeiro, March 2007 (BibTeX)

  12. F. J. Bouwens, M. Berekovic, A. Kanstein, G. N. Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array, proceedings of Int. Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 1-13, Rio de Janiero, Brazil, March 2007, LNCS 4419 (BibTeX)

  13. G. Kuzmanov, W.M. van Oijen, Floating-Point Matrix Multiplication in a Polymorphic Processor, International Conference on Field Programmable Technology (ICFPT), pp. 249--252, Kokurakita, Kitakyushu, JAPAN, December 2007 (BibTeX)

2006
  1. J.C.B. de Mattos, S. Wong, L. Carro, The Molen FemtoJava Engine, Proceedings of the 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP2006), pp. 19-22, USA, September 2006 (BibTeX)

  2. D.R.H. Calderón, S. Vassiliadis, Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASIC 06), pp. 311-316, Steamboat Springs-Colorado, USA, September 2006 (BibTeX)

  3. R. Chaves, G. Kuzmanov, L. A. Sousa, S. Vassiliadis, Rescheduling for Optimized SHA-1 Calculation, SAMOS Workshop on Computer Systems Architectures Modelling and Simulation, pp. 425-434, Samos, Greece, July 2006 (BibTeX)

  4. G. N. Gaydadjiev, S. Vassiliadis, SAD Prefetching for MPEG4 Using Flux Caches, Proceedings of the 6th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2006), pp. 248-258, Samos, Greece, July 2006, LNCS 4017 (BibTeX)

  5. A. Molnos, S. D. Cotofana, M.J.M. Heijligers, J.T.J. Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On­Chip Multi­Processors, Proceedings of the 2006 ACM International Conference on Computing Frontiers (CF’06), pp. 353 - 359, Ischia, Italy, May 2006 (BibTeX)

  6. S. Uhrig, S Maier, G. Kuzmanov, T. Ungerer, Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time Scheduling, Proceedings of the 13th Reconfigurable Architectures Workshop (RAW 2006), pp. 209, Rhodes Island, Greece, April 2006 (BibTeX)

  7. R. Chaves, G. Kuzmanov, S. Vassiliadis, L. A. Sousa, Reconfigurable Memory Based AES Co-Processor, Proceedings of the 13th Reconfigurable Architectures Workshop (RAW 2006), pp. 192, Rhodes Island, Greece, April 2006 (BibTeX)

  8. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing, Proceedings of Design, Automation and Test in Europe 2006 (DATE 06), pp. 369-374, Munich, Germany, March 2006 (BibTeX)

  9. A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Compositional, efficient caches for a chip multi-processor, Proceedings of Design, Automation and Test in Europe 2006 (DATE 06), pp. 345-351, Munich, Germany, March 2006 (BibTeX)

  10. S. Vassiliadis, G. Kuzmanov, S. Wong, E. Moscu Panainte, G. N. Gaydadjiev, K.L.M. Bertels, h Cheresiz, PISC: Polymorphic Instruction Set Computers, Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC 2006), pp. 274-286, Delft, The Netherlands, March 2006, LNCS 3985 (BibTeX)

  11. B. R. Donchev, G. Kuzmanov, G. N. Gaydadjiev, External Memory Controller for Virtex II Pro, in Proceedings of International Symposium on System-on-Chip 2006, pp. 37--40, November 2006 (BibTeX)

  12. B.G.C. de Ruijsscher, G. N. Gaydadjiev, J. Lichtenauer, E. A. Hendriks, FPGA accelerator for real-time skin segmentation, Proceedings of IEEE ESTIMedia 2006. Embedded Systems for Real Time Multimedia, pp. 93-97, Seoul, Korea, October 2006, ISBN 0-7803-9783-5 (BibTeX)

  13. R. Chaves, G. Kuzmanov, L. A. Sousa, S. Vassiliadis, Improving SHA-2 Hardware Implementations, Workshop on Cryptographic Hardware and Embedded Systems, CHES 2006, pp. 298-310, Yokohama, Japan, October 2006 (BibTeX)

2005
  1. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The Molen Media Processor: Design and Evaluation, Proceedings of the International Workshop on Application Specific Processors, WASP 2005, pp. 26--33, New York Metropolitan Area, USA, September 2005 (BibTeX)

  2. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Interprocedural Optimization for Dynamic Hardware Configurations, Proceedings of SAMOS 05, pp. 2-11, Samos, Greece, July 2005, Springer-Verlag Lecture Notes in Computer Science (LNCS) (BibTeX)

  3. C. J. Glossner, S. Dorward, S. Jinturkar, M. Moudgill, E. Hokenek, M. J. Schulte, S. Vassiliadis, Sandbridge Software Tools, Proceedings of SAMOS 05, pp. 269-278, Samos, Greece, July 2005, Springer-Verlag Lecture Notes in Computer Science (LNCS) (BibTeX)

  4. G. N. Gaydadjiev, S. Vassiliadis, Flux Caches: What Are They and Are They Useful?, Proceedings of the 5th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2005), pp. 93-102, Samos, Greece, July 2005, LNCS 3553 (BibTeX)

  5. D.R.H. Calderón, S. Vassiliadis, Reconfigurable Multiple Operation Array, Proceedings of SAMOS 05, pp. 22-31, Samos, Greece, July 2005, Springer-Verlag Lecture Notes in Computer Science (LNCS) (BibTeX)

  6. D.R.H. Calderón, S. Vassiliadis, Reconfigurable Universal SAD-Multiplier Array, Proceedings of the 2nd conference on Computing Frontiers, SESSION: Track 4: reconfigurable computing (part 1), pp. 72-76, Ischia, Italy, May 2005 (BibTeX)

  7. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Instruction Scheduling for Dynamic Hardware Configurations, Proceedings of Design, Automation and Test in Europe 2005 (DATE 05), pp. 100-105, Munich, Germany, March 2005 (BibTeX)

  8. A. Molnos, M.J.M. Heijligers, S. D. Cotofana, J.T.J. Eijndhoven, Compositional memory systems for multimedia communicating tasks, Proceedings of 2005 Design, Automation and Test in Europe (DATE 2005), pp. 932-937, Munich, Germany, March 2005 (BibTeX)

  9. Y. Dou, S. Vassiliadis, G. Kuzmanov, G. N. Gaydadjiev, 64-bit Floating-Point FPGA Matrix Multiplication, ACM/SIGDA Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA 2005), pp. 86--95, Monterey, CA, USA, February 2005 (BibTeX)

  10. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, The Molen Compiler Backend for Reconfigurable Architectures, Compiler and Architecture Seminar 2005, Haifa, Israel, December 2005, organized by IBM Research Lab in Haifa, Israel (BibTeX)

2004
  1. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, The PowerPC Backend Molen Compiler, in 14th International Conference on Field-Programmable Logic and Applications (FPL), pp. 434-443, Antwerp, Belgium, September 2004, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 3203 (BibTeX)

  2. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Visual Data Rectangular Memory, Proceedings of the 10th International Euro-Par Conference (Euro-Par 2004), pp. 760--767, Pisa, Italy, September 2004, LNCS 3149 (BibTeX)

  3. S. Jintukar, C. J. Glossner, V. Kotlyar, M. Moudgill, The Sandblaster automatic mulithtreaded vectorizing compiler, Proceedings International Signal Processing Conference, pp. 1-17, September 2004 (BibTeX)

  4. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Scene Management Models and Overlap Tests for Tile-Based Rendering, Proceedings of the EUROMICRO Symposium on Digital System Design, 2004 (DSD 2004)., pp. 424 - 431, Rennes, FRANCE, August 2004 (BibTeX)

  5. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Dynamic Hardware Reconfigurations: Performance Impact on MPEG2, Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, pp. 284-292, Samos, Greece, July 2004, July 2003, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 3133 (BibTeX)

  6. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The Virtex II Pro MOLEN Processor, Proceedings of the 4th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2004), pp. 192-202, Samos, Greece, July 2004, LNCS 3133 (BibTeX)

  7. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Memory Bandwidth Requirements of Tile-Based Rendering, Proceedings of the Third and Fourth International Workshops SAMOS 2003 and SAMOS 2004 (LNCS 3133), pp. 323-332, Samos, Greece, July 2004 (BibTeX)

  8. E Surducan, D. Iancu, C. J. Glossner, Modified printed dipole antennas for wireless multi band communication devices, Proceedings of the Int. Symposium on Electromagnetic Theory, pp. 1161-1163, Pisa, Italy, July 2004 (BibTeX)

  9. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, Logic-Enhanced Memory for 3D Graphics Tile-Based Rasterizers, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), pp. II-237 - II-240, Hiroshima, Japan, July 2004 (BibTeX)

  10. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, Efficient Hardware for Antialiasing Coverage Mask Generation, Proceedings of Computer Graphics International Conference 2004 (CGI 2004), pp. 257-264, Crete, Greece, June 2004 (BibTeX)

  11. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, GraalBench: A 3D Graphics Benchmark Suite for Mobile Phones, Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools, pp. 1-9, Washington, DC, USA, June 2004 (BibTeX)

  12. C. J. Glossner, M. Moudgill, D. Iancu, The sandbridge SDR Communications platform, Proceedings IEEE Symposium joint IST workshop on mobile future and symposium on trends in communications, pp. 1-8, Piscataway, June 2004 (BibTeX)

  13. D. Crisu, S. Vassiliadis, S. D. Cotofana, P. Liuha, Low Cost and Latency Embedded 3D Graphics Reciprocation, Proceedings of 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), pp. II-905 - II-908, Vancouver, Canada, May 2004 (BibTeX)

  14. B.H.H. Juurlink, P. J. de Langen, Dynamic Techniques to Reduce Memory Traffic in Embedded Systems, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 192-201, Ischia, Italy, April 2004 (BibTeX)

  15. P. J. de Langen, B.H.H. Juurlink, Reducing Traffic Generated by Conflict Misses in Caches, Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 235-239, Ischia, Italy, April 2004 (BibTeX)

  16. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The MOLEN Processor Prototype, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 296--299, Napa, CA, USA, April 2004 (BibTeX)

  17. M. J. Schulte, C. J. Glossner, S Mamidi, M. Moudgill, S. Vassiliadis, A low power multithreaded processor for baseband communication systems, Proceedings SAMOS workshop 2003-2004, pp. 393-402, March 2004 (BibTeX)

  18. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, GRAAL - A Development Framework for Embedded Graphics Accelerators, Proceedings of Design, Automation and Test in Europe (DATE'04), pp. 1366-1367, Paris, France, February 2004 (BibTeX)

  19. D. Iancu, H. Ye, Y. Abdelilah, S Emanoil, C. J. Glossner, On the performance of multiple OFDM receivers for DVB, Proceedings IEEE Symposium joint IST workshop on mobile future and symposium on trends in communications, pp. 1-4, Slovakia, December 2004 (BibTeX)

  20. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Multimedia Reconfigurable Hardware Design Space Exploration, Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2004), pp. 398-403, Cambridge, USA, November 2004 (BibTeX)

  21. I. Antochi, B.H.H. Juurlink, S. Vassiliadis, P. Liuha, Efficient Tile-Aware Bounding-Box Overlap Test for Tile Based Rendering, Proceedings 2004 International Symposium on System-on-Chip, pp. 165-168, Tampere, Finland, November 2004 (BibTeX)

  22. D. Iancu, C. J. Glossner, H. Ye, M. Moudgill, V. Kotlyar, Software rake receiver enhanced GPS system, Proceedings of the 2004 Software Defined Radio Technical Conference, pp. 97-105, Scottsdale, USA, November 2004 (BibTeX)

  23. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs, Lecture Notes in Computer Science (Proceedings of the Third International Workshop on Computer Systems: Architectures, Modeling and Simulation SAMOS III), pp. 168-177, Samos, Greece, November 2004 (BibTeX)

  24. D. Iancu, C. J. Glossner, M. Moudgill, Low delay spread multi-path cancellation of 3G WCDMA, Proceedings of the Winter Inter. Symposium on Information and Communication Technologies, pp. 428-433, Cancun, Mexico, November 2004 (BibTeX)

  25. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, 3D Graphics Tile-Based Systolic Scan-Conversion, Thirty-Eighth Asilomar Conference on, pp. 517 - 521, Pacific Grove, CA, USA, November 2004 (BibTeX)

  26. C. J. Glossner, M. J. Schulte, M. Moudgill, D. Iancu, T. Raja, G. Nacer, S. Vassiliadis, Sandblaster low-power multithreaded SDR baseband processor, Proceedings of the 3rd workshop on Applications Specific Processors, pp. 53-58, Stockholm, Sweden, October 2004 (BibTeX)

  27. S. Jinturkar, V Ramadurai, S Shamsunder, M. Moudgill, C. J. Glossner, Software centric approach to developing wireless applications, Proceedings of the 2004 Software Defined Radio Technical Conference, pp. 169-173, Scottsdale, USA, October 2004 (BibTeX)

  28. C. J. Glossner, Chirca, M. J. Schulte, H Wang, N Nasimzada, S Wang, J Hoane, G. Nacer, S. Vassiliadis, Sandblaster low power DSP, Proceedings of the IEEE 2004 custom integrated circuits conference, pp. 575-581, Orlando, USA, January 2004 (BibTeX)

  29. S Shamsunder, C. J. Glossner, Reduced complexity software receivers for TD-SCDMA downlink, Proceedings of the International Signal Processing Conference, pp. 1-5, January 2004 (BibTeX)

2003
  1. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiling for the Molen Programming Paradigm, Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL'03), pp. 900-910, Lisbon, Portugal, September 2003, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 2778 (BibTeX)

  2. G. Kuzmanov, S. Vassiliadis, Arbitrating Instructions in an -coded CCM, Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL'03), pp. 81-90, Lisbon, Portugal, September 2003, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 2778 (BibTeX)

  3. G. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, Loading rm-code: Design Considerations, Proceedings of the Third International Workshop on Computer Systems: Architectures, Modeling, and Simulation, pp. 11--19, Samos, Greece, July 2003, LNCS 3133 (BibTeX)

  4. S. Vassiliadis, G. N. Gaydadjiev, K.L.M. Bertels, E. Moscu Panainte, The Molen Programming Paradigm, Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp. 1-10, Samos, Greece, July 2003, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 3133 (BibTeX)

  5. D. Crisu, S. D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs, Proceedings of the Third International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS III), pp. 148-153, Samos, Greece, July 2003 (BibTeX)

  6. C. J. Glossner, S. Jinturkar, M. Moudgill, E. Hokenek, M. J. Schulte, S. Vassiliadis, Sandbridge Software Tools, Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp. 142-148, Samos, Greece, July 2003 (BibTeX)

  7. M. Sima, S. Vassiliadis, S. D. Cotofana, J. T. J. van Eijndhoven, Color Space Conversion for MPEG Decoding on FPGA-augmented TriMedia Processor, Proceedings of the 14th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2003), pp. 250-259, The Hague, The Netherlands, June 2003 (BibTeX)

  8. J. Nikara, S. Vassiliadis, FPGA-based Variable Length Decoders, Proceedings of VLSI-SOC 2003, pp. 437-441, Darmstadt, Germany, November 2003 (BibTeX)

  9. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K.L.M. Bertels, Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers, IEE FPGA Developer's Forum, London, United Kingdom, October 2003, (invited talk) (BibTeX)

  10. S. Vassiliadis, J.F. Collard, A. Bode, Parallel Computer Architecture and Instruction level Parallellism, Proceeedings EURO-PAR 2003 Parallel Processing, pp. 541-542, Berlin, January 2003, Springer Verlag (BibTeX)

2002
  1. S. Wong, S. Vassiliadis, S. D. Cotofana, A Sum of Absolute Differences Implementation in FPGA Hardware, in Proceedings of the 28th EUROMICRO Conference, pp. 183-188, Dortmund, Germany, September 2002 (BibTeX)

  2. C. J. Glossner, E. Hokenek, M. Moudgill, Wireless SDR solutions: The challenge and promise of next generation handsets, Proceedings of the CDC 2002 Communications Design Conference, pp. 1-6, San Jose, CA, USA, September 2002 (BibTeX)

  3. J. Nikara, S. Vassiliadis, J. Takala, M. Sima, P. Liuha, Parallel multiple-symbol variable-length decoding, Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 126-131, Freiburg, Germany, September 2002 (BibTeX)

  4. M. Sima, S. Vassiliadis, S. D. Cotofana, J. T. J. van Eijndhoven, K. A. Vissers, Field-Programmable Custom Computing Machines - A Taxonomy, Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL 2002). Reconfigurable Computing Is Going Mainstream, pp. 79-88, Montpellier, France, September 2002, Springer-Verlag, Lecture Notes in Computer Science (LNCS), Vol. 2438 (BibTeX)

  5. S. Wong, S. Vassiliadis, S. D. Cotofana, Future Directions of (Programmable and Reconfigurable) Embedded Processors, in Proceedings of the SAMOS 2002 Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, Samos, Greece, July 2002 (BibTeX)

  6. S. Wong, S. D. Cotofana, On Teaching Embedded Systems Design to Electrical Engineering Students, in Proceedings of 3rd International Conference on Information Communication Technologies in Education (ICICTE2002), pp. 505-515, Samos, Greece, July 2002 (BibTeX)

  7. M. Sima, E-J Pol, J. T. J. van Eijndhoven, S. D. Cotofana, S. Vassiliadis, Entropy Decoding on TriMedia/CPU64, Proceedings of the 2nd International Workshop on Systems, Architectures, MOdeling and Simulation (SAMOS 2002), Samos, Greece, July 2002, Leiden: SAMOS Initiative (BibTeX)

  8. E. G. Walters III, C. J. Glossner, M. J. Schulte, Automatic VHDL Model Generation of Parameterized FIR Filters, Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation, pp. 1-14, July 2002 (BibTeX)

  9. I. Lemberski, M. Koegst, S. D. Cotofana, B.H.H. Juurlink, FSM Non-minimal state encoding for low power, Proceedings 2002 23rd International conference on microelctronics, Vol. 2, pp. 605-609, Yugoslavia, May 2002 (BibTeX)

  10. I. Antochi, B.H.H. Juurlink, A. G. M. Cilio, P. Liuha, Trading efficiency for energy in a texture cache architecture, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems, pp. 189-196, Ischia, Italy, April 2002 (BibTeX)

  11. G. Kuzmanov, S. Vassiliadis, ALU Augmentation for MPEG-4 repetitive padding, MPCS'02 Proceedings of the 2002 Euromicro Conference on Massively-Parallel Computing Systems, Ischia, Italy, April 2002 (BibTeX)

  12. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 261-270, Napa Valley, California, USA, April 2002 (BibTeX)

  13. S. Wong, B. Stougie, S. D. Cotofana, Alternatives in FPGA-based SAD Implementations, in Proceedings of the 1st IEEE International Conference on Field-Programmable Technology (FPT2002), pp. 449-452, Hong Kong SAR, China, December 2002 (BibTeX)

  14. C. J. Glossner, E. Hokenek, M. Moudgill, Multi-threaded processor for software defined radio, Proceedings of the 2002 Software Defined Radio Technical Conference SDR'02, pp. 195-199, San Diego, CA, USA, November 2002 (BibTeX)

  15. G. Kuzmanov, S. Vassiliadis, Reconfigurable Repetitive Padding Unit, GLSVLSI '02 Proceedings of the 12th ACM Great Lakes symposium on, pp. 98-103, New York City, NY, USA, January 2002 (BibTeX)

2001
  1. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor, Proceedings of the IEEE International Conference on Computer Design (ICCD 2001), pp. 425-430, Austin, Texas, U.S.A., September 2001, Best Paper Award (BibTeX)

  2. S. Vassiliadis, G. Kuzmanov, S. Wong, MPEG-4 and the New Multimedia Architectural Challenges, in Proceedings of the 15th International conference on Systems for automation of engineering and research (SAER-2001), pp. 24-32, Varna, Bulgaria, September 2001 (BibTeX)

  3. P.I. Balzola, H. J. M. Schot, J Ruan, C. J. Glossner, E. Hokenek, Design alternatives for parallel saturating multioperand adders, Proceedings 2001 IEEE International conference on Computer design: VLSI in computers & Processors, pp. 172-178, Austin, Texas, USA, September 2001 (BibTeX)

  4. S. Vassiliadis, S. Wong, S. D. Cotofana, The MOLEN -coded Processor, in 11th International Conference on Field-Programmable Logic and Applications (FPL), Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2147, pp. 275-285, Belfast, UK, August 2001 (BibTeX)

  5. G. Kuzmanov, S. Vassiliadis, J. T. J. van Eijndhoven, A 2D adressing mode for multimedia applications, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, pp. 291-307, Samos, Greece, July 2001, (Lecture notes in computer science, 2268). Berlin: Springer (BibTeX)

  6. M. Sima, S. D. Cotofana, S. Vassiliadis, J. T. J. van Eijndhoven, K. A. Vissers, A Reconfigurable Functional Unit for TriMedia/CPU64: A Case Study, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS, pp. 224-242, Samos, Greece, July 2001, Springer-Verlag, Lecture Notes in Computer Science (LNCS), Vol. 2268 (BibTeX)

  7. S. Wong, S. Vassiliadis, S. D. Cotofana, Microcoded Reconfigurable Embedded Processors: Current Developments, Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2268, pp. 207-224, Samos, Greece, July 2001 (BibTeX)

  8. C. J. Glossner, D. Routenberg, M. J. Schulte, P.I. Balzola, Towards a Very High Bandwidth Wireless Battery Powered Devices, Proceedings. IEEE Computer Society Workshop on VLSI 2001: Emerging Technologies for VLSI Systems, pp. 3-9, Orlando, Canada, April 2001, IEEE Computer Society, Los Alamitos, 2001, ISBN: 0-7695-1056-6, cat. c, Projectcode: ET01-05 (BibTeX)

  9. M. Sima, S. D. Cotofana, J. T. J. van Eijndhoven, S. Vassiliadis, K. A. Vissers, An 8x8 IDCT Implementation on an FPGA-augmented TriMedia, Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2001), Rohnert Park, California, USA, April 2001 (BibTeX)

  10. S. Wong, S. D. Cotofana, S. Vassiliadis, Coarse Reconfigurable Multimedia Unit Extension, Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing (PDP 2001), pp. 235-242, Mantova, Italy, February 2001 (BibTeX)

2000
  1. G. G. Pechanek, S. Vassiliadis, The ManArrayTM embedded processor architecture, Proceedings of the 26th Euromicro Conference, pp. 348 - 355 vol.1, Maastricht , Netherlands, September 2000, IEEE Computer Society (BibTeX)

  2. M. Stanca, H. Corporaal, S. D. Cotofana, S. Vassiliadis, Hashed Addressed Caches for Embedded Pointer Based Codes, Proc. 6th Euro-Par 2000 Conference, pp. 278-284, Munich, Germany, August 2000, LNCS 1900, Springer, 2000 (BibTeX)

  3. S. Wong, S. D. Cotofana, S. Vassiliadis, Multimedia Enhanced General-Purpose Processors, Proceedings of the International Conference on Multimedia and Expo, pp. 1-4, New York City, NY, USA, July 2000 (BibTeX)

  4. S. Wong, S. D. Cotofana, S. Vassiliadis, General-Purpose Processor Huffman Encoding Extension, Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2000), pp. 158-163, Las Vegas, Nevada, March 2000 (BibTeX)

  5. A. Berlea, S. D. Cotofana, I. Athanasiu, C. J. Glossner, S. Vassiliadis, Garbage collection for the Delft Java Processor, Proceedings of the 8th IASTED International Conference on Applied Informatics (AI-2000), pp. 232-238, Innsbruck, Austria, February 2000 (BibTeX)

  6. M. Stanca, H. Corporaal, S. D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction, Proc. of IASTED Int. Conf on Applied Informatics 2000, Inssbruck, Austria, February 2000, IASTED, Annaheim, 2000 (BibTeX)

  7. C. J. Glossner, J. Moreno, M. Moudgill, J. Derby, E. Hokenek, D. Meltzer, U. Shvadron, M. Ware, Trends in Compilable DSP Architecture, proceedings. 2000 IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 181-199, Lafayette, USA, October 2000, EEE, Piscataway, 2000, ISBN: 0-7803-6488-0, cat. c, Projectcode: ET01-05 (BibTeX)

  8. D. Batten, S. Jinturkar, C. J. Glossner, M. J. Schulte, P. G. D'Arcy, A New Approach to DSP Intrinsic Functions, 33rd Annual Hawaii International Conference on System Sciences, pp. 1-10, Maui, Hawaii, January 2000, ISBN: 0-7695-0493-0 (BibTeX)

1999
  1. C. J. Glossner, S. Vassiliadis, Delft-Java Dynamic Translation, proceedings. Vol. 2. 25th Euromicro Conference, pp. 57-61, Milan, Italy, September 1999, IEEE, S.l., 1999, ISBN: 1089-6503 (BibTeX)

  2. E. A. Hakkennes, S. Vassiliadis, Hardwired Paeth codec for portable network graphics (PNG), Euromicro 99, pp. 318-325, Milan, Italy, September 1999 (BibTeX)

  3. G. G. Pechanek, S. Vassiliadis, N. Pitsianis, ManArray Processor Interconnection Network: An Introduction, Proceedings of the 5th International EuroPar Conference on Parallel Processing, pp. 761-765, September 1999, (Lecture Notes in Computer Science 1685) (BibTeX)

  4. D. Parson, P. Beatty, C. J. Glossner, B. Schlieder, A Framework for Simulating Heterogeneous Virtual Processors, Proceedings.32 nd Annual Simulation Symposium, pp. 58 -67, San Diego, Los Alamitos, April 1999 (BibTeX)

  5. N. Yadav, M. J. Schulte, C. J. Glossner, Parallel Saturating Fractional Arithmetic Units, Proceedings of the Ninth Great Lakes Symposium on VLSI, pp. 214-217, Ypsilanti, MI, USA, March 1999, Projectcode: ET01-05 (BibTeX)

  6. D. Batten, S. Jinturkar, C. J. Glossner, M. J. Schulte, R. Peri, P. G. D'Arcy, Interaction between Optimizations and a New Type of DSP Intrinsic Function, Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT'99), Orlando, Forida, USA, November 1999 (BibTeX)

1998
  1. S. Jinturkar, J. Thilo, C. J. Glossner, P. G. D'Arcy, S. Vassiliadis, Profile Directed Compilation in DSP Applications, Proceedings of the International Conference on Signal Processing Applications and technology (ICSPAT'98), September 1998 (BibTeX)

  2. C. J. Glossner, S. Vassiliadis, Delft-JAVA Link Translation Buffer, Euromicro 98, pp. 221-228, Vasteras, Sweden, August 1998, ISBN: 0-8186-8646-4 (BibTeX)

  3. S. Vassiliadis, E. A. Hakkennes, S. Wong, G. G. Pechanek, The Sum-of-Absolute-Difference Motion Estimation Accelerator, in Proceedings of the 24th Euromicro Conference, pp. 559-566, Vasteras, Sweden, August 1998 (BibTeX)

  4. C. J. Glossner, J. Thilo, S. Vassiliadis, Java Signal Processing: FFT's with Bytecodes, Proceedings of ACM 1998 Workshop on Java for High-Performance Network Computing, pp. 239-243, Palo Alto, California, USA, February 1998 (BibTeX)

1997
  1. C. J. Glossner, S. Vassiliadis, The Delft-Java Engine: An Introduction, Lecture Notes In Computer Science, Third International Euro-Par Conference (Euro-Par'97 Parallel Processing), pp. 766-770, Passau, Germany, August 1997 (BibTeX)

  2. E. A. Hakkennes, S. Vassiliadis, S. D. Cotofana, Fast Computation of Compound Expressions in Two's Complement Notation, Proceedings of the 15th IMACS World Congress on Scientific Computation, Modeling and Applied Mathematics, pp. 689-694, Berlin, August 1997 (BibTeX)


since 26 Sep 2006.