| ADRES : IMEC, Architecture for Dynamically Reconfigurable Embedded System. | |
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ADRIATIC
: Intracom, IMEC, Intracom, VTT Electronics, STMicroelctronics, NOKIA Advanced Methodology for Designing ReconfIgurable SoC and Application-Targeted IP-entities in wireless Communications. |
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ALCHEMY : INRIA, Architectures, Languages and Compilers to Harness the End of Moore Years. |
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AMDREL
: Democritus University of Thrace, IMEC, Intracom, STMicroelctronics, Architectures and Methodologies for Dynamic REconfigurable Logic. |
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Arachne : TU Delft, Network Processor Architecture. |
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ARTEMIS : TU Delft, Leiden, U.Amsterdam, Architecture, Programming and Exploration of Embedded Systems. |
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ATC : U. of Cantabria, Computer Architecture, Parallel Computing Group. |
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BRASS
: Berkeley Reconfigurable Architectures, Systems, & Software. |
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Chameleon : TU Twente, Reconfigurable computing in hand-held multimedia computers. |
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Delft Workbench : TU Delft, Semi-automatic Tool Platform for Reconfigurable Computing. |
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DRP : NEC, Dynamically Reconfigurable Processor (DRP, Commercial product). |
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EXSITE
: Royal Institute of Technology, Stockholm, Network on Chip Architecture Template for Integrated Telecommunication Systems. |
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FLASH : Stanford, FLexible Architecture for SHared memory multiprocessor. |
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Hydra
: Standford, A Next Generation Microarchitecture. |
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Imagine
: Standford, The Imagine Stream Architecture for 3D graphics and image processing. |
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Merrimac
: Stanford Streaming Supercomputer Project. |
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MOLEN
: TU Delft, MOLEN Reconfigurable Processors. |
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MorphoSys
: U.Washington, Coarse-Grained Adaptable Architectures. |
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PipeRench
: Carnegie Mellon's Reconfigurable Computer. |
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Pixel-Plane
: UNC, High-Performance Graphics Architectures. |
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PreMaDoNa
: TU Eindhoven, Predictable Matching of Demands on Networked Architectures. |
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RAMIS
: TU Muenchen, Reconfigurable Architectures Microprocessors Systems Design. |
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| RaPiD : U.Washington, Coarse-Grained Adaptable Architectures. | |
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RAW : MIT, raw Architecture Workstation. |
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ROCCC : UC Riverside, Riverside Optimizing Compiler for Configurable Computing. |
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SESAME : Simulation of Embedded System Architectures for Multi-level Exploration. |
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SPADE : System-level Performance Analysis and Design space Exploration. |
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SPAM
: Princeton, MIT, UCB, Aachen, UNICAMP, Synopsys, Fujitsu, Rockwell Retargetable Optimizing Compiler for Embedded Processors. |
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TOTEM : U.Washington, Tools to Automatically Generate Domain-specific Reconfigurable Architectures. |
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TRIPS : UT Austin, The Tera-op Reliable Intelligently adaptive Processing System. |
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Virtual Computer Corporation : The Reconfigurable Computer Company. |
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XPUTER
: Kaiserslautern U., Deterministically Data-driven Non-von-Neumann Computational Machine. |
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XiRisc
: U. Bologna., RISC Reconfigurable Processor . |
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Zippy
: ETH, A Novel Dynamically Reconfigurable Processor. |
since 26 Sep 2006.