SHA512 core
This hybrid (hardware/software) SHA512 implementation has been design with the MOLEN processor. The SHA512 core with Initialization Vector loading capability has been introduced in the MOLEN processor as a CCU. This prototype (available for free download from this page) has been implemented on the XUP-V2P(with a XCVP30) prototyping board. For more extensive information on the SHA512 core and the MOLEN processing paradigm consult the references.

MOLEN processor Specifications:
  • Program memory: 64KB in BRAM
  • Data memory: 64KB in BRAM
  • Maximum PowerPC clock rate 300MHz*
  • Memory clock 100MHz*
SHA512 core in the MOLEN processor:
  • 512 and 384 data hashing
  • Allows external Initialization Vectors
  • Throughput: 1.2 Gbit/s @100MHz
  • Device utilization: 1806 Slices

* frequencies for chip speed grade -7

References:
  1. R. Chaves, G.K. Kuzmanov, L. A. Sousa, S. Vassiliadis, Improving SHA-2 Hardware Implementations, Workshop on Cryptographic Hardware and Embedded Systems (CHES 2006), pp. 298-310, Yokohama, Japan, October 2006 (BibTeX)
  2. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, G.K. Kuzmanov, E. Moscu Panainte, The MOLEN Polymorphic Processor, IEEE Transactions on Computers, pp. 1363- 1375, November 2004, Volume 53, Issue 11 (BibTeX)
  3. E. Moscu Panainte, K. Bertels, S. Vassiliadis, The PowerPC Backend MOLEN Compiler, in 14th International Conference on Field-Programmable Logic and Applications (FPL), pp. 434-443, Antwerp, Belgium, September 2004, Springer-Verlag Lecture Notes in Computer Science (LNCS), vol. 3203 (BibTeX)
  4. G.K. Kuzmanov, G. N. Gaydadjiev, S. Vassiliadis, The Virtex II Pro MOLEN Processor, Proceedings of the 4th International Workshop on Computer Systems: Architectures, Modelling, and Simulation (SAMOS 2004), pp. 192-202, Samos, Greece, July 2004, LNCS 3133 (BibTeX)
  5. S. Vassiliadis, S. Wong, S. D. Cotofana, The MOLEN ρμ-coded Processor, in 11th International Conference on Field-Programmable Logic and Applications (FPL), Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2147, pp. 275-285, Belfast, UK, August 2001 (BibTeX)
  6. NIST, Secure Hash Standard (SHS), FIPS 180-2, tech. rep., National Institute of Standards and Technology, August, 2002.

Design Tools Required to test the core: None

Design Tools Required to modify the software: Online compiler (not supported anymore due to work on upgraded version) and ISE 6.3i design environment


Downloads:


The MOLEN PPC C compiler
Compile your SHA512 application here (not supported anymore due to work on upgraded version)
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SHA512 core on the MOLEN Processor for Virtex II Pro FPGA
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XUP V2P board files - xc2vp30 chip; 100 MHz Download (< 500 kB)
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Contact Person: Ricardo Chaves


Cryptographic cores page