The Virtex II Pro prototype is intended for researchers and designers, both from the academia and the industry, willing to accelerate software applications with reconfigurable hardware. The design framework allows a designer to concentrate on the design of the reconfigurable hardware accelerators (CCUs) as the implemented prototype infrastructure controls all synchronization tasks and the communications between the software (i.e., the PowerPC) and the reconfigurable accelerator. The prototype computational scheme guarantees performance efficient operation and the proposed methodology allows short design cycle.
Prerequisites:
- The application program code in C language as an input to the Molen PowerPC compiler (support discontinued due to upgrade work) .
- The function of interest for implementation in reconfigurable hardware identified in the software code.
- A functionally equivalent and synthesizable HDL description (VHDL or Verilog) of the identified software function.
What else do you need?
Install the design tools required and follow some useful links, closely related to the recommended modular design flow by Xilinx. Make sure you have a Xilinx Virtex II Pro evaluation boards. Our designs have been tested on the following boards: XUP V2P (xc2vp30 chip);
ADM- XPL (xc2vp20 chip).
Mapping the prototype design on other Virtex II Pro based boards is also possible, but would require deeper understanding of the Xilinx tools.
Design Tools Required:
- ISE 6.3i design environment
Useful Links:
- Modular Design Overview: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/dev/dev0025_7.html
