This file describes the modular design flow for 
the Molen Virtex II Pro prototype implemented on 
XUP V2P prototyping board


A. Assumptions:

   - Familiarity with Xilinx ISE 6.3i/8.1/8.2 - the appropriate package should be installed.
   - Familiarity with Xilinx Modular Design Flow 
     (For more detailed information on Modular Design, 
      please see Chapter 4 of the Xilinx Development System 
      Reference Guide. Online web-based version on:
      http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/dev/dev0026_7.html)
   - The proposed design has been tested on a Xilinx 
     XUP V2P prototyping board with a xc2vp30 chip. 
     Other boards will require additional considerations.
   - The design comprises three basic modules: 
     a) clocks generator (clk_gen),
     b) custom computing unit(s) (CCU_XXX)
     c) Molen infrastructure with BRAM memories (MOLEN_bram)
   - Assume directory structure as presented in Section B.
   

B. Directory structure:

MOLEN_ROOT (distribution)
|
---top
|   |
|   ---Initial
|   |
|   ---assemble
|   |
|   ---syn
|
---modules
|   | 
|   ---clk_gen
|   |   |
|   |   ---clk_gen_syn
|   |   |
|   |   ---clk_gen_impl
|   |
|   ---CCU_XXX (Module(s) to be implemented by the user)
|       |
|       ---CCU_XXX_syn
|       |
|       ---CCU_XXX_impl
|
---pim 
|   |
|   ---molen_top (included in the distribution)
|   |
|   ---ccu (created during the design flow)
|   |
|   ---clk_gen (created during the design flow)
|
---SW


C. Initial Budgeting Phase (see Xilinx Modular Design)

1. Run Project Navigator and open project "MOLEN_ROOT\top\syn\molen_AD.npl". 
2. Synthesize the top design (molen_ad.vhd).
NOTE!!! To resynthesize molen_ad.vhd uncomment the appropriate lines in 
MOLEN_ROOT\top\Initial.bat or rerun Steps 1-2. 
3. Execute MOLEN_ROOT\top\Initial.bat
4. In the automatically opened floorlan editor:
 - discard the warning that 
   "The design has area group(s) with more than one range constraint.";
 - in menu Floorplan->Distribution Options, 
   check the box "Autofloorplan as needed".
 - from menu File->Read Constraints... 
   read file MOLEN_ROOT\top\Initial\molen_AD.ucf.
 - if necessary (e.g., if your new CCU design does not fit, 
   see Section E), reassign chip areas for the three modules: 
   clk_gen_i", "CCU_i", and "molen_top_i" either using the 
   floorplan editor graphical interface (recommended) or by editing
   MOLEN_ROOT\top\Initial\molen_AD.ucf in text-mode.
   Make sure the assigned areas do not overlap.
 - !!!If a board, different from Alpha Data ADM-XPL, is used, check 
   carefully its implemented pin-out and use floorplanner to 
   change the pin assignments accordingly!!!
   !!!The FPGA chip, however, must be the same, i.e., xc2vp30.!!!
 - save into file MOLEN_ROOT\top\Initial\molen_AD.ucf.
 - exit the floorplanner. 
5. Edit file MOLEN_ROOT\top\Initial\molen_AD.ucf as follows:
 - Delete line (if presented):
   AREA_GROUP "AG_molen_top_i" RANGE = MULT18X18......;
 - Modify the following lines (if not already done) like this:
   AREA_GROUP "AG_molen_top_i" RANGE = RAMB16_X1Y1:RAMB16_X7Y13 ; 
   AREA_GROUP "AG_CCU_i" RANGE = RAMB16_X0Y0:RAMB16_X0Y13;
   AREA_GROUP "AG_CCU_i" RANGE = MULT18X18_X0Y0:MULT18X18_X0Y13;


D. Building and embedding your own CCU.
   (Use the example CCU as a template. 
   Strictly implement the CCU interface utilized.)
   NOTE!!! By default PPC assumes big endian memory alignment-
   keep that in mind, when designing your own CCU, which accesses 
   data memory locations shared with the PPC. 

1. Create an appropriate directory structure as shown below.
   (follow these directions strictly, because the command
    batch files assume this recommended directory structure)

   MOLEN_ROOT (distribution)
   |
   ---modules
       |
       ---CCU_XXX
           |
           ---CCU_XXX_syn
           |
           ---CCU_XXX_impl
2. Synthesize your source files (e.g. CCU_XXX.vhd) into subfolder 
   CCU_XXX_syn WITHOUT I/O PORTS INSERTION. 
   - If you are using project navigator, I/O insertion is banned 
     as follows: 
     select entity "CCU" and select menu Process->Properties..., 
     then select tab Xilinx Specific Options and uncheck the box 
     "Add I/O Buffers".
   - to ban I/O insertion in a third party synthesizer, 
     consult the Xilinx Modular Design Documnetation. 
   NOTE!!! The top entity name should be CCU 
  (see for example CCU_count.vhd).

3. Copy MOLEN_ROOT\modules\CCU_count\CCU_count_active.bat into 
   MOLEN_ROOT\modules\CCU_XXX\CCU_XXX_active.bat and edit it in 
   accordance with your actual module name CCU_XXX (i.e., 
   substitute CCU_count with CCU_XXX).
   Note!!! If you have synthesized your CCU design using XST, 
   the synthesis file should be CCU.ngc. If you employed other 
   synthesis tools, you should translate the obtained EDIF file 
   (CCU.edf) into CCU.ngo using ISE6.3i EDIF netlist readers 
   (check the ISE6.3i documentation) and replace CCU.ngc with 
   CCU.ngo in file CCU_XXX_active.bat. 
   Note!!!Should your design comprises several .ngc and/or .ngo 
   files, modify CCU_XXX_active.bat so that all *.ngc and *.ngo 
   files are first copied into subfolder 
   MOLEN_ROOT\modules\CCU_XXX\CCU_XXX_impl.

4. Execute CCU_XXX_active.bat

5. Incorporate the design into the entire design flow by 
   introdicing the name CCU_XXX wherever applicable in cleanup.bat
   and run_flow.bat 
   (the current *.bat templates assume CCU_count for the name CCU_XXX)


E. Compilation with the CE web-based PowerPC backend compiler 
   and linking of the application software.
   
   1. Open the Compiler URL: 
   http://ce.et.tudelft.nl/~molen/cgi-bin/read.cgi
   2. Upload the desired application C file according to the 
      instructions in the Compiler readme.txt file.
      (For the counter example 
       upload MOLEN_ROOT\SW\counter_example_SW.c,
       change the Input XR Address to 0x56, 
       the Outout XR Address to 0x5B,
       and type in "count" for the Pragma NAME)
   3. Check "Generate ELF file"
   4. Download the generated executable.elf file into 
      subfolder MOLEN_ROOT\SW\


F. Active module implementation and final assembly

1. Execute MOLEN_ROOT\run_flow.bat
2. Read log file MOLEN_ROOT\flow.log to check the design flow reports.
3. A correct design flow should generate a bitstream file named 
   download.bit in the directory MOLEN_ROOT.


G. Downloading the bitstream into the FPGA and running the design.

1. Connect the serial communication port of the board to a PC COM port.
2. On the PC, open a terminal session (e.g., HyperTerminal in MS Windows), 
   set it to 19200bps, 8 data bits, No parity, 1 Stop bit, no Flow control.
3. In MOLEN_ROOT run:
   impact -batch download.cmd
   The program has to start executing in the terminal window.


H. To cleanup the project files in MOLEN_ROOT run:
   cleanup.bat