------------------------------------------------------------------
                  The Molen Compiler v1.0alpha
                        September 2005

                     Elena Moscu Panainte
                    elena@ce.et.tudelft.nl

                     Computer Engineering
                           TU Delft
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Introduction
------------

The Molen compiler is an optimizing compiler for reconfigurable computing paradigm. The research is part of two projects of Computer Engineering group, namely MOLEN () and Delft WorkBench(). 

The main goal is to provide compilation support for reconfigurable architectures and to develop new optimization techniques that take advantage of the new features (such as partial and runtime configuration) of the state-of-the-art reconfigurable architectures.


Compilation Flow
----------------


          .C file
             |
             |
             V
     ------------------     
     |     SUIF       |
     |  MachineSUIF   |
     ------------------
     |PowerPC backend |
     | RC extensions  |
     |RC Optimization |
     ------------------
             |
     .s file |
             V
     ------------------
     | GNU Assembler  |
     |  GNU Linker    |
     ------------------
             |
             |
             V 
           .elf file 

References:
SUIF - http://suif.stanford.edu/suif/suif2/
MachineSuif - http://www.eecs.harvard.edu/hube/research/machsuif.html
GNU binutils - http://www.gnu.org/software/binutils/

 
          
Input C Application and Compilation 
---------------------------------

1) Kernel identification 
The kernel that is executed on the reconfigurable hardware should be a whole function. The definition of the kernel function  should be preceeded be a pragma annotation followed by "call_fpga" and the name of the hardware operation associated with this function.

Example:
#pragma call_fpga dct
int my_kernel( char * input, int size, int par1){
.........
}  

2) Kernel replacement
In the compilation stage, all function calls of the kernel function  will be replaced with the approriate instructions for execution on the reconfigurable hardware. 

3) Parameter passing
The function parameters are moved in special registers called Exchange Registers (XRs) in the same order as in the prototype of the kernel function. Each parameter should occupy one XR and they should be placed in consecutive order. The first XR should be specified in the input form.

4) Returning the results
The result is returned in the XR  which is specified in the input form.

NOTE:
- each file is compiled separately
- when parameters/results do not fit in one XR, pointers to memory addresses should be used.

 
 

Online compiler Usage
---------------------


1) Input C files

- for only one C file: the text of the C program should be copyed in the  textarea after the message "Please, introduce your C file here (max 30Kb)". Note: The C file should not be larger than 30Kb.

- for more C/header files:  a tgz archive (tar -czvf) with all C/header files should be uploaded using the button under the message "Or pick the .tgz archive with all C files (max 30Kb)"
Note: - the size of the tgz archive should be less than 30Kb.
      - the files included in the archives should be all ONLY C files. 
      - the tgz archive should not contain directories or subdirectories. 


2) FPGA description file

- "Input XR": the hexa number of the first XR which is used for passing parameters to the reconfigurable hardware.
Note: The total number of available XRs is 512.
 
- "Output XR": the hexa number of the XR which is used for passing returning the computed result from the reconfigurable hardware.
Note: The total number of available XRs is 512.

- "Pragma NAME:  the name of the hardware operation associated with the kernel function.
Note: the name should be not longer than 32 chars.

Example of generated FPGA description file:

NO_XRS = 512
XRin = 0x56
XRout = 0xA7

Op_NAME = encrypt
SET_ADDR = 0x24677A10
EXEC_ADDR = 0x1A000031
END_OP


3) Compiler Output

-  "Generate Assembly file": stop before  assembly/linking phase.
Note: If the input C files where included in a tgz archive, the resulted .s files are included in a tgz archive. 

-  "Generate ELF file": the compiler will produce an ELF executable file using the GNU assembler and linker. 



Miscellaneous
-------------

The main limitations for PowerPC backend: 
- floating point operations are not handled in the current version. The target IBM PowerPC 405 processor does not support floating point operations, which should be emulated in software. The software emulation will be available soon in the Molen compiler.
- definition of functions with variable number of parameters is not supported.
- struct/union type for the result return by a function is not supported due to a limitation in the SUIF/MachineSUIF.

For profiling purposes, the following functions are by default included in the generated executables:

- void init_timer() - reset the timer
- void read_timer() - print the timer = the number of cycles counted from the last timer reset operation



Copyright and Disclaimer
------------------------

This software is provided under the terms described in the 
Copyrights from http://ce.et.tudelft.nl/~molen/html/Copyright.html. The users are kindly invited to send any bug, corrections and/or enhancements that should be done the the current version.