There is a wide range of cost/performance tradeoffs for implementing DSP algorithms into silicon, especially when targeting diverse technologies like FPGAs and ASICs. Finding the optimal implementation usually involves exploring parallel vs. serial architectures and will be highly dependent on the available resources, speed, and architecture of the technology. This session will explore how some of the commmonly used optimizations work and how they can be applied automatically to high-level algorithm models using Synplicity's Synplify DSP tool. The seminar will include examples in wireless communications and will benefit engineers who are interested in:

• Methods to rapidly describe algorithms and explore speed/area optimization tradeoffs
• Creating algorithms and IP that are easily portable and optimized across vastly different FPGA technologies

Date: WEDNESDAY 29th August, 2007
Time: 13:00 - 17:00 (Lunch included)
Registration: Registration Form
Location: Movenpick Hotel, Amsterdam

Pierluigi Lo Muzio, graduated in Electronics Engineering at the University of Pisa (IT) and joined Philips Research in 1988. After 1 year working on HD-TV in Nat Lab Eindhoven, Pierluigi continued in Monza (IT), actively contributing to several European Research Projects in the role of DSP Project Leader. Pierluigi has spent many years working with well known European firms such as ST. Microelectronics and Thomson Multimedia as DSP Architect and Project Leader in the fields of optical recoding, wireless systems, digital televisions, and FPGAs. Pierluigi has authored several papers presented at International Conferences and has won some patents in the DSP field. In 2005 Pierluigi joined Synplicity as DSP Specialist, in the European Sales Headquarter, Munich. Currently Pierluigis role is to manage the deployment of the new Synplicity ESL products in the European market.