FPL 2007 is proud to have the following
keynote speakers:
- Ajay V. Bhatt on the Intel Geneseo Project. Abstract
- John Wawrzynek, University of California-Berkeley. Abstract
- Mark Dickinson, Vice President of Altera's European Technology Center Abstract
- Steve Trimberger, Xilinx, Abstract
|
| CONFERENCE PROGRAM (Preliminary) |
The preliminary conference program can be downloaded HERE.
|
| |
MONDAY- August 27,
2007 |
| 08:30 |
OPENING |
| 09:00 |
Keynote 1 - Ajay V. Bhatt,
Intel |
| 10:00 |
Break
& Poster Session 1 |
| 10:40 |
M1.A APPLICATIONS I |
M1.B DESIGN TOOLS & COMPILERS I |
M1.C MULTICORE SYSTEMS |
| |
Session Chair: Pete Sedcole |
Session Chair:
Joao Cardoso |
Session
Chair: Nick Carter |
10:40
-
11:00 |
Design Space Exploration of the
European Option Benchmark Using HyperStreams
Gareth William Morris, and Matt Aubury |
Array Synthesis
in SystemC Hardware Compilation
Johan Ditmar and Steve McKeever |
A
Many-Core Implementation based on the Reconfigurable Mesh Model
Heiner Giefers and Marco Platzner |
11:00
-
11:20 |
Accelerating a
Medical 3D Brain MRI Analysis Algorithm using a High-Performance
Reconfigurable Computer
Jahyun Koo, Alan Evans, and Warren Gross |
Floating-Point
Trigonometric Functions for FPGAs
Jérémie Detrey and Florent de Dinechin
|
An
FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor
Systems
Taeweon Suh, Shih-Lien Lu, and Hsien-Hsin Lee |
11:20
-
11:40 |
Soft-Hard 3D
FD-TD Solver for Non Destructive Evaluation
Fernando Pardo, Paula López, and Diego Cabello
|
A Method for
Fast Hardware Generation at Run-time
Karel Bruneel, Peter Bertels, and Dirk
Stroobandt
|
RAMP
Blue: A Message-Passing Manycore System in FPGAs
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg
Gibeling, and Pierre-Yves Droz |
| 11:40 |
Break & Poster Session 2 (INCLUDING PHD FORUM) |
| 12:00 |
LUNCH |
| 13:10 |
M2.A APPLICATIONS II |
M2.B
HIGH PERFORMANCE COMPUTING |
M2.C RUN-TIME SUPPORT I |
| |
Session Chair: Tulika Mitra |
Session Chair: Oliver Diessel |
Session
Chair: Juanjo Noguera |
13:10
-
13:30 |
A Radio
Astronomy Correlator Optimized for the Xilinx Virtex-4 SX FPGA
Ludovico de Souza, John Bunton, Duncan
Campbell-Wilson, Roger Cappallo, and Bart Kincaid |
Bringing
High-Performance Reconfigurable Computing to Exact Computations
Esam El-Araby, Ivan Gonzalez, and Tarek
El-Ghazawi
|
Supporting
High Level Language Semantics Within Hardware Resident Threads
Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron,
Fabrice Baijot, Seth Warn, and David Andrews |
13:30
-
13:50 |
TANOR: A Tool
for Accelerating N-Body Simulations on Reconfigurable Plarform
J. S. Kim, P. Mangalagiri, K. Irick, M. Kandemir, V.
Narayanan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, and X. Sun |
Applying
Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems
Yi-Gang Tai, Chia-Tien Dan Lo, and Kleanthis
Psarris
|
Formal
Modeling of Process Migration
Aric Blumer, Henning Mortveit, and Cameron
Patterson
|
13:50
-
14:10 |
Performance
Modeling of 2D Cellular Automata on FPGA
Syed Murtaza, Alfons G. Hoekstra, and Peter M.A.
Sloot
|
Multi-processor
System-level Synthesis for Multiple Applications on Platform FPGA
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman,
and Henk Corporaal |
Dynamic
Cache Switching in Reconfigurable Embedded Systems
John Shield, Peter Sutton, and Philip Machanick
|
| 14:10 |
Break
& Poster Session 3 |
| 14:50 |
M3.A PLACEMENT & ROUTING I |
M3.B BIOLOGY APPLICATIONS I |
M3.C POWER I |
| |
Session Chair: Mike Hutton |
Session Chair: Marco
Platzner |
Session
Chair: Dimitrios Soudris |
14:50
-
15:10 |
Improving
Timing-Driven FPGA Packing With Physical Information
Doris T. Chen, Kristofer Vorwerk, and Andrew Kennings |
A
Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem
Shuichi Watanabe, Junji Kitamichi, and Kenichi Kuroda |
Pre-Route
Interconnect Capacitance and Power Estimation in FPGAs
Shilpa Bhoj and Dinesh Bhatia |
15:10
-
15:30 |
Clock-Aware
Placement for FPGAs
Julien Lamoureux and Steven Wilton
|
High
Speed Tablation System using an FPGA designed for Distribution Tables of
Frequent DNA Subsequences
Yoshiki Yamaguchi, Tsutomu Maruyama, Fumikazu Konishi,
and Akihiko Konagaya |
Exploiting
Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling
in Dynamically Reconfigurable Systems
Pao-Ann Hsiung and Chih-Wen Liu |
15:30
-
15:50 |
Fast On-Line
Task Placement and Scheduling on Reconfigurable Devices
Xue Gong Zhou, Ying Wang, Xun Zhang Huang, and Cheng
Lian Peng |
Discrete
Event Simulation of Molecular Dynamics with Configurable Logic
Josh Model and Martin Herbordt
|
A
Power Estimation Model for an FPGA-based Softcore Processor
Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred
Glesner, Holger Blume, and Tobias Noll |
| 15:50 |
Break
& Poster Session 4 |
| 16:30 |
AMSTERDAM CANALS TOUR - BY CANAL BOAT - sponsored by ACE (http://www.ace.nl) |
| 19:00 |
RECEPTION CITY HALL
AMSTERDAM |
| 20:00 |
(END OF MONDAY PROGRAM) |
| |
TUESDAY - August 28, 2007 |
| 08:30 |
Keynote 2 - Mark
Dickinson, Altera European Technology Center |
| 09:30 |
Break
& Poster Session 5 |
| 10:10 |
T1.A
COMMUNICATION & SECURITY |
T1.B ARCHITECTURE I |
T1.C IMAGE & VIDEO PROCESSING |
| |
Session Chair: Tarek El-Ghazawi |
Session Chair:
Martin Schoeberl |
Session
Chair: Fernando Goncalves |
10:10
-
10:30 |
A
Software Defined Radio Application Utilizing Modern FPGAs and NoC
Interconnects
Graham Schelle, Jeff Fifield, and Dirk Grunwald
|
Embedded
Programmable Logic Core Enhancements for System Bus Interfaces
Bradley Quinton and Steven Wilton
|
An
Area-efficient Alternative to Adaptive Median Filtering in FPGAs
Zdenek Vasicek and Lukas Sekanina
|
10:30
-
10:50 |
Intellectual
Property Protection of HDL IP Cores through Automated Signature Hosting
Encarnacion Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Baese, and Antonio Lloris |
Domain-Specific
Hybrid FPGA: Architecture and Floating Point Applications
Chun Hok Ho, Chi Wai Yu, Philip H.W. Leong, Wayne Luk,
and Steven J.E. Wilton |
An
Efficient Implementation of a 2D DWT on FPGA
Michael Wisdom and Peter Lee
|
10:50
-
11:10 |
Physical
Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection
Jorge Guajardo, Sandeep Kumar, Geert-Jan Schrijen, and
Pim Tuyls |
Improving
Pipelined Soft Processors with Multithreading
Martin Labrecque and Gregory Steffan
|
H.264/AVC
In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction
Cell Based Architecture
Adam Major, Ioannis Nousias, Sami Khawam, Mark
Milward, Ying Yi, Mark Muir, and Tughrul Arslan |
| 11:10 |
Break
& Poster Session 6 |
| 11:50 |
T2.A POWER II |
T2.B BIOLOGY
APPLICATIONS II |
T2.C DESIGN TOOLS & COMPILERS II |
| |
Session Chair: Eduardo Boemo |
Session Chair: Roger Woods |
Session Chair:
Christian Hochberger |
11:50
-
12:10 |
On
the Feasibility of Early Routing Capacitance Estimation for FPGAs
Jonathan Clarke, George Constantinides, and Peter
Cheung
|
FPGA
Implementation of a Data-Driven Stochastic Biochemical Simulator with the
Next Reaction Method
M. Yoshimi, Y. Iwaoka, Y. Nishikawa, T. Kojima, Y.
Osana, A. Funahashi, N. Hiroi, Y. Shibata, N. Iwanaga, H. Yamada, H. Kitano,
and H. Amano |
Disjoint Pattern
Enumeration for Custom Instructions Identification
Pan Yu and Tulika Mitra
|
12:10
-
12:30 |
Adaptive
Thermoregulation for Applications on Reconfigurable Devices
Phillip Jones, James Moscola, Young Cho, and John
Lockwood
|
GENDIV
- A Hardware Algorithm for Intron and Exon String Detection in DNA
Chains
Octavian Creţ, Zsolt Mathe, Paul Ciobanu, Sonia
Mărginean, and Cristian Leluţiu |
Fast and
Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical
Synthesis Tools
Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, and Yajun
Ha
|
12:30
-
12:50 |
Power
Reduction in Network Equipment through Adaptive Partial Reconfiguration
Juanjo Noguera and Irwin O. Kennedy
|
A
Unified Streaming Architecture for Real Time Face Detection and Gender
Classification
Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan,
Rajeev Sharma, Hankyu Moon, and Satish Mummareddy |
An Execution
Model for Hardware/Software Compilation and its System-Level
Realization
Holger Lange and Andreas Koch
|
| 12:50 |
LUNCH |
| |
TUESDAY - August 28, 2007 (continuation) |
| 14:00 |
Keynote 3 - John
Wawrzynek, University of California-Berkely |
| 15:00 |
Short
Break |
| 15:15 |
T3.A PLACEMENT &
ROUTING II |
T4.B ARCHITECTURE II |
T3.C DESIGN TOOLS & COMPILERS III |
| |
Session Chair: Andreas Koch |
Session Chair:
Michael Hübner |
Session Chair: Fadi J. Kurdahi |
15:15
-
15:35 |
Module Graph
Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA
Device
Shannon Koh and Oliver Diessel
|
Virtualization
on the Tartan Reconfigurable Architecture
Mahim Mishra and Seth Goldstein
|
A Design Methodology for
Communication Infrastructures on Partially Reconfigurable FPGAs
Jens Hagemeyer, Boris Kettelhoit, Markus Koester, and
Mario Porrmann |
15:35
-
15:55 |
Layered Approach
to Intrinsic Evolvable Hardware using Direct Bitstream Manipulation of Virtex
II Pro Devices
Rashad Oreifej, Rawad Al-Haddad, Heng Tan, and Ronald
DeMara
|
Time Predictable
CPU and DMA Shared Memory Access
Christof Pitter and Martin Schoeberl
|
Efficient
FPGA-based multipliers for F_3^97 and F_3^(6*97)
Jamshid Shokrollahi, Elisa Gorla, and Christoph
Puttmann
|
15:55
-
16:15 |
A Generalized
and Unified SPFD-based Rewiring Technique
Pongstorn Maidee and Kia Bazargan
|
Improving
External Memory Access for Avalon Systems on Programmable Chips
Hendrik Eeckhaut, Mark Christiaens, and Dirk
Stroobandt
|
Efficient
mapping of a Kalman filter into an FPGA using Taylor Expansion
Yang Liu, Christos-Savvas Bouganis, and Peter Y.K.
Cheung
|
| 16:15 |
Break
& Poster Session 7 |
| 16:50 |
T4.A PLACEMENT & ROUTING III |
T4.B NETWORKS ON CHIP |
T4.C EU SESSION |
| |
Session Chair: Sinan Kaptanoglu |
Session
Chair: Christophe Bobda |
Session Chair: Georgi
Kuzmanov |
16:50
-
17:10 |
Implementation
of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial
Self- Reconfiguration on Xilinx Spartan III FPGAs
Katarina Paulsson, Michael Hübner, Günther Auer,
Michael Dreschmann, and Jürgen Becker |
artNoC
- A Novel Multi-Functional Router Architecture for Organic Computing
Christian Schuck, Stefan Lamparth, and Jürgen
Becker
|
The
ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous
Systems
A. Herrholz, F. Oppenheimer, P.A. Hartmann, A.
Schallenberg, W. Nebel, C. Grimm, M. Damm, J. Haase, F. Brame,
F. Herrera, E. Villar, I. Sander, A. Jantsch, A.-M Fouilliart, and M.
Martinez |
17:10
-
17:30 |
L4: An
FPGA-Based Accelerator for Detailed Maze Routing
John Nestor and Jeremy Lavine |
A
Time-Triggered Network-on-Chip
Martin Schoeberl |
HARTES
Toolchain Early Evaluation: Profiling, Compilation and HDL Generation
K. Bertels, G. Kuzmanov, E. Moscu Panainte, G.
Gaydadjiev, Y. Yankova, V.M. Sima, K. Sigdel, R. Meeuws, S. Vassiliadis |
17:30
-
17:50 |
Improving
Annealing Via Directed Moves
Kristofer Vorwerk, Andrew Kennings, Jonathan Greene,
and Doris T. Chen
|
A
Temporal Correlation Based Port Combination Methodology for Networks-on-chip
on Reconfigurable Systems
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, and
Hideharu Amano |
MORPHEUS:
Heterogeneous Reconfigurable Computing
F. Thoma, M. Kühnle, P. Bonnot, E. Moscu Panainte, K. Bertels, S. Goller, A. Schneider, S. Guyetant, E. Schüler, K.D.
Müller-Glaser, J. Becker |
17:50
-
18:10 |
|
Router Design
for Application Specific Networks-on-Chip on Reconfigurable Systems
Mário Véstias and Horácio Neto |
On-line
Routing of Reconfigurable Functions for Future Self-Adaptive Systems -
Investigations within the ÆTHER Project
K.Paulsson, M.Hübner, J. Becker, J.-M. Philippe, C.
Gamrat |
| |
|
| 19:30 |
CONFERENCE DINNER at
FIFTEEN |
| |
WEDNESDAY - August 29, 2007 |
| 09:00 |
Keynote 4 - Steve Trimberger, Xilinx |
| 10:00 |
Break |
| 10:40 |
W1.A DESIGN TOOLS AND COMPILERS IV |
W1.B RUN-TIME SUPPORT II |
|
| |
Session Chair:
Michael Hübner |
Session Chair:
George A. Constantinides |
|
10:40
-
11:00 |
Equivalence
Verification of FPGA and Structured ASIC Implementations
Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail
Iotov, Enoch Julias, and Kumara Tharmalingam |
ReconOS: An
RTOS supporting Hard- and Software Threads
Enno Lübbers and Marco Platzner
|
|
11:00
-
11:20 |
Statistical
Generic And Chip-Specific Skew Assignment for Improving Timing Yield of
FPGAs
Satish Sivaswamy and Kia Bazargan
|
The
Design of Multitasking Based Applications on Reconfigurable Instruction Cell
Based Architectures
Wei Han, Ioannis Nousias, Mark Muir, Tughrul Arslan,
and Ahmet T. Erdogan |
|
11:20
-
11:40 |
Fault Models and
Yield Analysis for QCA-based PLAs
Michael Crocker, Michael Niemier, and X. Sharon
Hu
|
Monte
Carlo Logarithmic Number System for Model Predictive Control
Panagiotis Vouzis, Sylvain Collange, Mark Arnold, and
Mayuresh Kothare |
|
| 11:45 |
PRESENTATION OF FPL 2008
& CLOSING |
| 12:30 |
LUNCH OFFERED BY
SYNPLICITY FOR THE SYNPLICITY WORKSHOP PARTICIPANT |
| 14:00 |
SYNPLICITY
WORKSHOP
(at conference hotel) |
| - |
| 17:00 |
|
| |
THURSDAY - August 30, 2007 |
| 09:00 |
|
| - |
XILINX WORKSHOP (Day 1) |
| 17:00 |
(at Delft University of
Technology, Delft, The Netherlands) |
| |
FRIDAY - August 31, 2007 |
| 09:00 |
|
| - |
XILINX WORKSHOP (Day 2) |
| 17:00 |
(at Delft University of
Technology, Delft, The Netherlands) |
|
|
|
|
|
POSTER SESSIONS |
|
| |
MONDAY - August
27, 2007 |
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Dynamic Voltage
Scaling in a FPGA-Based System-on-Chip
Jose Luis Nunez-Yanez, Vassilios Chouliaras, and Jiri
Gaisler |
Multiplexer-based Routing Fabric for Reconfigurable Logic
Martijn Bennebroek and Alexander Danilin |
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically
Reconfigurable Architecture
Mahendra Kumar, Angamuthu Ganesan, Sundeep Singh, Frank
May, and Jürgen Becker |
Implementation on FPGA of a LUT-based atan(Y/X) Operator
Suitable for Synchronization Algorithms
Roberto Gutierrez and Javier Valls |
Efficient Priority-Queue Data Structure for Hardware
Implementation
Andrew Morton, Jeffrey Liu, and Insop Song |
Compact AES-based Architecture for Symmetric Encryption, Hash
Function, and Random Number Generation
Ralf Laue, Oliver Kelm, Sebastian Schipp, Abdulhadi
Shoufan, and Sorin A. Huss |
Design of a Hardware Accelerator for Fingerprint Alignment
Mariano Fons, Francisco Fons, Enrique Canto, and
Mariano Lopez |
An FPGA Implementation of Multiple Sequence Alignment Based on
Carrillo-Lipman Method
Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, and
Akihiko Konagaya |
An FPGA Solver for Very Large SAT Problems
Kenji Kanazawa and Tsutomu Maruyama |
A Multi-objective GA based Physical Placement Algorithm for
Heterogeneous Dynamically Reconfigurable Arrays
Ioannis Nousias, Sami Khawam, Mark Milward, Mark Muir,
and Tughrul Arslan |
P
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Aggressive Loop
Pipelining for Reconfigurable Architectures
Ricardo Menotti, Eduardo Marques, and João Cardoso
(PhD Forum) |
Comrade - A Compiler for Adaptive Computing Systems Using a
Novel Fast Speculation Technique
Hagen Gädke and Andreas Koch
(PhD Forum) |
Self-Healing Circuits for Space-Applications
Thomas Panhofer and Martin Delvai (PhD Forum) |
Automatic Software Hardware Co-Design for Reconfigurable
Computing Systems
Proshanta Saha (PhD Forum) |
VPH - A Tool for Exploring Hybrid FPGAs
Chi Wai Yu (PhD Forum) |
Hybridthreads Compiler: Generation of Application Specific
Hardware Thread Cores from C
Jim Stevens |
Wires On Demand: Run-Time Communication Synthesis for
Reconfigurable Computing
Peter Athanas, John Bowen, Tim Dunham, Cameron
Patterson, Justin Rice, Matt Shelburne, Jorge Suris, Mark Bucciero, and
Jonathan Graf |
A Behavioral Synthesis Approach for Distributed Memory FPGA
Architectures
Ashutosh Pal and M. Balakrishnan |
Mapping VLIWxSIMD Processor on an FPGA: Scalability and
Performance
Micha Nelissen, Kees van Berkel, and Sergei Sawitzki |
An Automatic Compilation Framework for Configurable
Architectures
Alberto Gallini, Lorenzo Pavesi, Alberto Rosti, and
Sara Bocchio |
A High Throughput Area Time Efficient Pseudo Uniform Random
Number Generator based on the TT800 Algorithm
Vinay Sriram and David Kearney |
Dynamic Partial FPGA Reconfiguration in a Prototype
Microprocessor System
Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo,
Walid Najjar, and Frank Vahid |
P
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3 |
A
Load/Store Unit for a Memcpy Hardware Accelerator
Stamatis Vassiliadis, Filipa Duarte, and Stephan Wong |
Incremental Fault Emulation
Jan Torben Weinkopf, Klaus Harbich, and Erich Barke |
A Novel Motion Estimation Power Reduction
Technique
Graeme Stewart, David Renshaw, and Martyn Riley |
A Variable Grain Logic Cell Architecture for
Reconfigurable Logic Cores
Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori
Matsuyama, Masahiro Iida, and Toshinori Sueyoshi |
A High Speed License Plate Recognition System
on an FPGA
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai,
Daisuke Konno, Tomomichi Nanba, and Yoshiaki Ajioka |
Redefine: Architecture of a SOC Fabric for
Runtime Composition of Computation Structures
A N Satrawala, Keshavan Varadarajan, Mythri Alle, S K
Nandy, and Ranjani Narayan |
Implementation of a 2-D 8x8 IDCT on the
Reconfigurable Montium Core
Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink,
Pascal T. Wolkotte, and Gerard J.M. Smit |
A Reprogrammable and Scalable Multimedia
Traffic Generator/Monitor on FPGA
José M. Claver, Pau Agustí, Germán León, and Manel Canseco |
C++-based Design Flow for Reconfigurable Image
Processing Systems
Rob Beun, Irek Karkowski, and Maarten Ditzel |
A Floating-point Extended Kalman Filter
Implementation for Autonomous Mobile Robots
Vanderlei Bonato, Eduardo Marques, and George A.
Constantinides |
Efficient External Memory Interface for
Multi-processor Platforms Realized on FPGA Chips
Hristo Nikolov, Todor Stefanov, and Ed Deprettere |
Hardware/Software Process Migration and RTL
Simulation
Aric Blumer and Cameron Patterson |
| |
Implementation
of a Barotropic Operator for Ocean Model Simulation using a Reconfigurable
Machine
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, and
Duncan A. Buell |
P
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Evolutionary
Search Applied to Reconfigurable Analogue Control
Kester Clegg, Susan Stepney, and Tim Clarke |
Soft IP Core Implementation of Recursive Least
Squares Filter using only Multiplicative and Additive Operators
Gaye Lightbody, Roger Woods, and Jonathan Francey |
Characterizing Effective Memory Bandwidth of
Designs with Concurrent High-Performance Computing Cores
Andrew Schmidt and Ron Sass |
A Design Flow to Map Parallel Applications onto
FPGAs
Sébastien Le Beux, Philippe Marquet, and Jean-Luc Dekeyser |
A Hybrid Reconfigurable Cluster-on-Chip
Architecture With Message Passing Interface For Image Processing
Applications
Irfan Syed, John Williams, and Neil Bergmann |
Novel Multi-layer Floorplanning for
Heterogeneous FPGAs
Love Singhal and Elaheh Bozorgzadeh |
Automatic Accuracy-Guaranteed Bit-Width
Optimization for Fixed and Floating-Point Systems
William G. Osborne, Ray C.C. Cheung, Jose G.F.
Coutinho, Wayne Luk, and Oskar. Mencer |
Accelerating Microblaze Floating Point
Operations
Jiri Kadlec, Roman Bartosinski, and Martin Danek |
Analysis of Kernel Effects on Optimisation
Mismatch in Cache Reconfiguration
John Shield, Peter Sutton, and Philip Machanick |
High Level Power Optimization by Type Inference
on the Generation of Application Specific Circuits on FPGAs
José M. Claver and Germán León |
Dynamically Reconfigurable Dataflow
Architecture for High-performance Digital Signal Processing on Multi-FPGA
Platforms
Sven-Ole Voigt and Thomas Teufel |
| |
RIC
Fast Adder and its Set Tolerant Implementation in FPGAs
Eduardo Mesquita, Helen Franck, Luciano Agostini, and José Luís Güntzel |
| |
TUESDAY
- August 28, 2007 |
P
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5 |
Solving
RC5 Challenges with Hardware -- a Distributed.net Perspective --
Guerric Meurice de Dormale, John Bass, and Jean-Jacques
Quisquater |
High Level Abstraction Language as an
Alternative to Embedded Processors for Internet Packet Processing in
FPGA
Tomas Dedek, Tomas Marek, and Tomas Martinek |
Exploring Alternative 3D FPGA Architectures:
Design Methodology and CAD Tool Support
Kostas Siozios, Kostas Sotiriadis, Vassilis F.
Pavlidis, and Dimitrios Soudris |
AdaBoost ENGINE
Pavel Zemcík and Martin Zádník |
An FPGA Based Memory Efficient Shared Buffer
Implementation
Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir
Sezer, Mike Hutton, and Kevin Cackovic |
Efficient Modeling and Floorplanning of
Embedded-FPGA Fabric
Sumanta Chaudhuri, Jean-Luc Danger, and Sylvain Guilley |
A New Scalable
Hardware Architecture For RSA Algorithm
Tamer Güdü |
Implementation of Low Frequency Finite State
Machines Using the SRL16 Primitive
Irwin Kennedy |
Run-time Partial Reconfiguration for Removal,
Placement and Routing on the Virtex-II-Pro
Stefan Raaijmakers and Stephan Wong |
Dynamic Reconfiguration Management based on a
Distributed Object Model
Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, and Juan Carlos López |
Circuit Switched Run-Time Adaptive
Network-on-Chip for Image Processing Applications
Lars Braun, Michael Hübner, Jürgen Becker, Thomas
Perschke, Volker Schatz, and Stefan Bach |
An OCM-based Shared Memory Controller for
Virtex 4
Bas Breijer, Filipa Duarte, and Stephan Wong |
| |
DWARV:
DelftWorkBench Automated Reconfigurable VHDL Generator
Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi
Gaydadjiev, Yi Lu, and Stamatis Vassiliadis |
| |
Accelerating
Tool Path Computing in CAD/CAM: An FPGA Architecture for Turning Lathe
Machining
Antonio Jimeno-Morenilla, Antonio Martinez, Sergio Cuenca, and Jose Luis Sánchez-Romero |
P
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Exploiting
Analog and Digital Reconfiguration for Smart Sensor Interfacing
Diego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, and Encarnación Castillo |
SoPC architecture for a Key Point Detector
Harding Djakou Chati, Felix Mhlbauer, Tim Braun,
Christophe Bobda, and Karsten Berns |
A Pipeline Implementation of a Watershed Algorithm on FPGA
Dang Ba Khac Trieu and Tsutomu Maruyama |
FPGA Implementation of 64-Bit Exponential Function for HPC
Ernest Jamro, Kazimierz Wiatr, and Maciej Wielgosz |
A Graphical Model-Level Debugger for Heterogenous Reconfigurable
Architectures
Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser,
and Jürgen Becker |
A Run-Time Reconfigurable Processor for Video Motion
Estimation
Miguel Ribeiro and Leonel Sousa |
Configuration Management in the Context of Self Adaptive
Systems
Yvan Eustache and Jean-Philippe Diguet |
A Quantitative Model for Hardware/Software Partitioning
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi
Gaydadjiev, and Stamatis Vassiliadis |
Caching in Real-time Reconfiguration Port Scheduling
Florian Dittmann and Stefan Frank |
Effective Automatic Memory Allocation Algorithm Based on
Schedule Length in Cycles in a Novel C to FPGA Compiler
Kristopher D. Peterson and Justin L. Tripp |
Wirelength Prediction for FPGAs
Audip Pandit and Ali Akoglu |
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable
FPGAs
Slavisa Jovanovic, Camel Tanougast, Christophe Bobda,
and Serge Weber |
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System-level
Modelling and Analysis of Embedded Reconfigurable Cores for Wireless
Systems
Ali Ahmadinia, Balal Ahmad, Ahmet Erdogan and Tughrul
Arslan |
A Resource optimized SoC Kit for FPGAs
Gerald Hempel and Christian Hochberger |
A Banded Smith-Waterman FPGA Accelerator for Mercury
BLASTP
Brandon Harris, Arpith Jacob, Joseph Lancaster, Jeremy
Buhler, and Roger Chamberlain |
Compression System for the Phonocardiographic Signal
F. J. Toledo-Moreo, A. Legaz, J.J. Martínez-Álvarez,
J. Martinez-Alajarín, and R. Ruiz-Merino |
RLS Lattice Algorithm with Order Probability Evaluation as an
Accelerator for the Microblaze Processor
Zdenek Pohl and Milan Tichy |
NOC Implementation in FPGA using Torus Topology
Angelo Kuti Lusala, Phillipe Manet, Bertrand Rousseau,
and Jean-Didier Legat |
Microarchitectural Enhancements for Configurable Multi-Threaded
Soft Processors
Roger Moussali, Nabil Ghanem, and Mazen Saghir |
FPGA based Sparse Matrix Vector Multiplication using Commodity
DRAM Memory
David Gregg, Colm McSweeney, Ciaran McElroy, Fergal
Connor, Seamas McGettrick, David Moloney, and Dermot Geraghty |
A Novel Event Based Simulation Algorithm for Sequential Digital
Circuit Simulation
Karthick Parashar and Nitin Chandrachoodan |
Design Methodology and Trade-offs Analysis for Parameterized
Dynamically Reconfigurable Processor Arrays
Yohei Hasegawa and Hideharu Amano |
An FPGA based Open Source Network-on-Chip Architecture
Andreas Ehliar and Dake Liu |
FlowContext: Flexible Platform for Multigigabit Stateful Packet
Processing
Martin Kosek and Jan Korenek |
A Combining Technique of Rate Law Functions for a Cost-effective
Reconfigurable Biological Simulator
Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata,
Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima,
Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, and Kiyoshi
Oguri |
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