Moore’s law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. I/O interconnects are on a similar growth path of increasing performance and efficiency. As computing requirements become more complex, new strategies evolve to provide the performance necessary for data- and calculation-intensive applications. A growing such strategy is the use of specialized accelerators to enhance the performance of specific tasks or functions. Broadly speaking, an accelerator is a device that attaches to a computing system, providing optimal performance at reduced cost and/or power for a specialized task. Examples of emerging applications for which accelerators may be suitable are photorealistic graphics, financial simulation, and climate modeling. The development of specialized application accelerators is happening today. However, they do not share a common attach point, and have no common architecture or programming model. An industry framework that economically and efficiently enables specialized acceleration is highly desirable.

This talk will focus on a new architectural framework for the attached application accelerators called Geneseo. The talk will provide an overview of the Geneseo interconnect and software architecture and provide insight in to proposed improvements in available bandwidth, latency, efficiency and software interface.

Ajay Bhatt is an Intel Fellow in the Digital Enterprise Group and chief I/O architect. Bhatt is responsible for future platform and I/O interconnects directions for Intel. This role involves leading the definition of next-generation Application Accelerator Architecture called Geneseo and I/O technologies across the market segments internally and within the industry.

Bhatt is an industry-recognized expert in I/O technologies and was instrumental in the development and proliferation of USB, AGP4X and PCI Express as ubiquitous industry standards. Bhatt joined Intel in 1990 as a senior staff architect on the chipset architecture team in Folsom.

Bhatt received his bachelor’s degree in electrical engineering from the M.S. University, Baroda, India, in 1980. He received his master’s degree from The City University of New York in 1984. Bhatt holds nine U.S. patents and has few patents in various stages of development.

In 1998, 2003 and 2004 Bhatt was nominated to take part in a Distinguished Lecture Series at leading universities in the United States and Asia. He received an Achievement in Excellence Award for his contribution in PCI Express specification development in 2002. Bhatt is Fellow-in-residence for Intel India.