Current Projects

Delft Workbench group participates in the following projects:

hArtes: Holistic Approach for Real Time Embedded Systems
Other participants in the project: Atmel Roma, Scaleo Chip, Politecnico di Milano, Imperial College, French National Institute for Research in Computer Science and Control (INRIA), Leaff Engineering, Universita di Ferrara, FAITAL, Univerisita Politecnica delle Marche, Thomson R&D France, Fraunhofer Gesellschaft zur Foe¶rderung der angewandten Forschung e.V. (FHG-IGD), Universite d'Avignon et des Pays de Vaucluse, Thales Communications SA

hArtes aims to lay the foundation for a new holistic (end-to-end) approach for complex real-time embedded system design, with the latest algorithm exploration tools and reconfigurable hardware technologies. The proposed approach will address, for the first time, optimal and rapid design of embedded systems from high-level descriptions, targeting a combination of embedded processors, digital signal processing and reconfigurable hardware. We will develop modular and scalable hardware platforms that can be reused and re-targeted by the tool chain to produce optimized real-time embedded products. The results will be evaluated using advanced audio and video systems that support next-generation communication and entertainment facilities, such as immersive audio and mobile video processing. Innovations of our approach include: (a) support for both diagrammatic and textual formats in algorithm description and exploration, (b) a framework that allows novel algorithms for design space exploration, which aims to automate design partitioning, task transformation, choice of data representation, and metric evaluation for both hardware and software components, (c) a system synthesis tool producing near-optimal implementations that best exploits the capability of each type of processing element; for instance, dynamic reconfigurability of hardware can be exploited to support function upgrade or adaptation to operating conditions. From the application point of view, the complexity of future multimedia devices is becoming too big to design monolithic processing platforms. This is where the hArtes approach with reconfigurable heterogeneous system becomes vital.

hArtes is financially supported by Sixth Framework Programme.


MORPHEUS: Multipurpose Dynamically Reconfigurable Platform for Intensive and Heterogeneous Processing
Other participants in the project: THALES Research & Technology, Deutsche Thomson-Brandt GmbH, Intracom SA, Lucent Technologies Network Systems GmbH, Thales Optronics SA, STMicroelectronics Srl, PACT XPP Technologies AG, M2000, Associated Compiler Experts, CriticalBlue, Universit� Karlsruhe, Commissariat �l'�ergie Atomique - LIST, Universit�de Bretagne Occidentale, Universita di Bologna, ARTTIC

The large-scale deployment of Embedded Systems, through Cooperating Objects for example, is raising new demanding requirements in terms of computing performance, cost-efficient development, low power, functional flexibility and sustainability. This results in an increasing complexity of the platforms and an enlarging design productivity gap: current solutions are out of breath while current development and programming tools do not support the time-to-market needs.

MORPHEUS copes with these challenges by developing a global solution based on a modular SOC platform providing the disruptive technology of embedded dynamically reconfigurable computing completed by a software (SW) oriented design flow. These "Soft Hardware (HW)" architectures will enable huge computing density improvements (GOPS / Watt) by a factor of x100, reuse capabilities by x5, flexibility by more than 100 and time to market divided by 2 thanks to a convenient programming toolset.

Hence, MORPHEUS ambitions are to establish the European foundation for a new concept of flexible "domain focused platforms", positioned between general purpose flexible HW and general purpose processors.

This will be achieved within a 3-years project providing:
  • A modular silicon demonstrator composed of complementary run-time reconfigurable building blocks to address the different types of application requirements
  • The corresponding integrated design flow supporting the fast exploration of HW and SW alternatives
The suitability and the efficiency will be validated by a set of complementary test cases. The dissemination through silicon offer and supporting tools (baseline for further commercial products) will be completed by specific training and broad information to address the necessary cultural change. This will be performed by:
  • A consortium where many partners are already involved in bilateral cooperation,
  • A 2-step process to monitor the final content of the project according to state of the art evolution and first results.
MORPHEUS is financially supported by Sixth Framework Programme.


RCOSY: Reconfigurable COSY
Other participants in the project: Associated Compiler Experts

A recent and increasingly popular trend in industry is the use of reconfigurable processing units (RPU) in embedded or general purpose processing systems. There are many reasons that explain the popularity of this particular technology. First, it allows for a wide variety of functional behaviour that can be dynamically configured in real time. Secondly, it provides the designer-manufacturer with additional instruments to optimise a number of (cost) parameters such as energy consumption, silicon area. Third, it provides massive parallel computing power. Reconfigurable hardware co-existing with a core processor has been proposed as a good candidate for speeding up processor performance. Such an approach can be very promising; however the organization of such a hybrid processor can be viewed mostly as an open topic.

In this project, we propose to develop a semi-automatic tool to assist the designer in determining what functions should be considered for reconfigurable or mixed system implementation. This tool will be integrated in the COSY COMPILER SYSTEM of the company ACE. We will integrate useful existing tools and develop novel approaches to improve the identification process. We intend to develop a high-level to high-level restructuring compiler that will consider input programs written in a high level language and will generate an annotated program with augmentations and instrumentations to provide information for reconfigurable computing. Using this information, we will construct a cost model that allows to make performance predictions based on a set of design parameters.

The Molen Programming Paradigm, developed at the CE laboratory in collaboration with other Dutch research groups, will be used allowing a smooth integration of reconfigurable computing units in traditional uni-processor machines. The Molen Programming Paradigm consists of an extension of the instruction set with a "SET" and "EXECUTE" instruction to separate the context setting from the actual execution phase.

RCOSY is financially supported by ACE and STW.