| If you are an MSc student and you are interested in any of the following projects for your final thesis, please contact Koen Bertels (K.L.M.Bertels@its.tudelft.nl) or Elena Moscu Panainte (E.Panainte@its.tudelft.nl) |
| Currently there are two on-going master projects: |
Code ProfilingExisting applications need to be analysed in order to identify interesting candidates for mapping on the FPGA. This analysis should be done using a set of criteria. These criteria should look at issues such as I/O, branches, arithmetic operations, etc. and result in a decision model that can be applied on any application. The outcome of this decision model should be a list of candidate functions that can be mapped on an FPGA. The goal of the research is to propose such a decision model and to validate it focusing on a limited number of applications and doing preliminary calculations for performance improvement. |
Library of FPGA configurationsA important aspect in designing a new architecture, the designer is confronted with a large variety of design choices. The goal of this research is to make a first step toward supporting this design space exploration process by establishing a library of (existing) FPGA mappings which can then be used for real evaluation on the Xilinx Virtex Pro. The data from these evaluations can then be used to construct a model that allows the designer to evaluate different designs prior to real implementation. |